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Housekeeping

Housekeeping. teams—end of class Example verilog code (alter) Example altera report Lab Monday: you will be asked to show: -- one or more reports --one or more verilog modules --one or more simulation. Processors (ISA, RTL levels); Instruction cycle; interrupts Computer Processor Basics

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Housekeeping

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  1. Housekeeping teams—end of class Example verilog code (alter) Example altera report Lab Monday: you will be asked to show: -- one or more reports --one or more verilog modules --one or more simulation

  2. Processors (ISA, RTL levels); Instruction cycle; interrupts Computer Processor Basics ISA (Instruction Set Architecture) RTL (Register Transfer Language) Main references: Peckol, Chapters 1-3 Patt and Patel, Introduction to Computing Systems (slides from NC State) Fig. 01-00

  3. “Machine” categories • FSM • Stack machine • Turing machine • von Neumann architecture • Harvard architecture Harvard memory: separation of program, data Von Neumann memory program and data share one memory program data

  4. I/O Popped Item (from “Top”) Control (fsm) Combinational Logic “Top” Stack

  5. Registers Cache Main Memory (RAM) (Virtual Storage) {Hard Disk, Secondary Devices} (Actual “RAM” Hierarchy)

  6. fig_01_05 Some processor options (note firmware) 1. Microprocessor-based system fig_01_05 2. Microcontroller-based system Fig. 1-05 components integrated into one unit) fig_01_07 DSP (A/D, D/A; high speed—video, audio, images fig_01_06

  7. Instruction Set Architecture • ISA = All of the programmer-visible components and operations of the computer • memory organization • address space -- how may locations can be addressed? • addressibility -- how many bits per location? • register set • how many? what size? how are they used? • instruction set • opcodes • data types • addressing modes • ISA provides all information needed for someone that wants towrite a program in machine language(or translate from a high-level language to machine language).

  8. Example 1:LC-3 (Patt) Overview: Memory and Registers • Memory • address space: 216 locations (16-bit addresses) • addressability: 16 bits • Registers • temporary storage, accessed in a single machine cycle • accessing memory generally takes longer than a single cycle • eight general-purpose registers: R0 - R7 • each 16 bits wide • how many bits to uniquely identify a register? • other registers • not directly addressable, but used by (and affected by) instructions • PC (program counter), condition codes

  9. LC-3 Overview: Instruction Set • Opcodes • 15 opcodes • Operate instructions: ADD, AND, NOT • Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI • Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP • some opcodes set/clear condition codes, based on result: • N = negative, Z = zero, P = positive (> 0) • Data Types • 16-bit 2’s complement integer: (q: how does 2’s c arithmetic work?) • Addressing Modes • How is the location of an operand specified? • non-memory addresses: immediate, register • memory addresses: PC-relative, indirect, base+offset

  10. Example: NOT (Register) Note: Src and Dstcould be the same register.

  11. Example: ADD/AND (Register) this zero means “register mode”

  12. DATA: DATA TYPES fig_01_08 NUMERIC --Unsigned integer --Signed integer (2’s complement, sign-magnitude, fixed point, etc.) --Floating point: 3 components: sign exponent mantissa fig_01_08 NONNUMERIC --address --character Q: what common data type is not named? Is it “missing”?

  13. Instructions—ISA level • Instruction coding: • HLL (high level language, C, C++ , e.g.) • assembly language (ISA) • machine language (can work at any level; high level allows faster but less efficient coding) IEEE Standard 694-1985—IEEE standard for microprocessor assembly language—used for examples in text

  14. operator addr mode operand(s) Instruction coding: Fields: operator, operands (type of addressing) Example: 32 bits 3 bits: opcode 2 bits: address mode (e.g. direct, indirect, indexed, immediate) 27 bits: for addressing operand (s) Expanding opcode (example): 000-110xxxx…xxx: 2 operands 1110xxx…xxx: 1 operand 1111xxx…xxx: no operand (e.g., HALT)

  15. Example instruction formats fig_01_13 fig_01_14 fig_01_13 fig_01_15

  16. fig_01_42 Typical ALU and registers fig_01_42

  17. fig_01_16 Data movement instructions: source / destination fig_01_16

  18. Addressing modes: Immediate: MOVE A, #BH; Direct: MOVE OPR1, OPR2; Indirect: MOVE OPR1, *myVarPtr; MOVE *OPR1, *OPR1; MOVE *OPR1, **yPtr; Register direct: MOVE Reg1, Reg2; Register indirect: MOVE Reg1, *Reg2; Indexed (loops): MOVE Reg1, OPR2[REG2]; PC relative (loops,e.g.; offset can be negative): ADD PC, [Reg1]; Example: what is the difference between Y, *Y, **Y fig_01_12 fig_01_12 Indirect addressing—myVarPtr holds address or myVar

  19. Addressing examples: fig_01_21 fig_01_21

  20. fig_01_22 fig_01_22

  21. fig_01_23 fig_01_23

  22. fig_01_24 fig_01_24

  23. fig_01_25 Control instructions Control can be: sequential (default) loop (pre or posttest) branch: go to conditional (if, if-else,, case, branch on condition) procedure or function call [interrupt or exception] change in control flow, e.g., I/O device ready Unusual event, e.g., overflow or undefined instruction

  24. Example of conditional statements: C / assembly language: fig_01_31 fig_01_31 fig_01_32

  25. Looping: example fig_01_34 fig_01_34 fig_01_35

  26. Function or procedure call: Must store return address, pass information back and forth What are standard parameter passing methods? fig_01_36 fig_01_36 fig_01_37

  27. fig_01_39 Stack: common way to handle procedure / function calls Q: what are two alternative methods for handling function / procedure calls? Which methods facilitate recursion? fig_01_39

  28. fig_01_40 Function call: example: fig_01_40 fig_01_41

  29. LC-3 Data Path Filled arrow = info to be processed. Unfilled arrow = control signal.

  30. Instruction Processing Cycle Fetch instruction from memory Q: what about interrupts? Decode instruction Evaluate address Fetch operands from memory Execute operation Store result

  31. fig_01_46 Different viewpoint: RTL: register-transfer language level fig_01_46

  32. fig_01_52 RTL VIEW fig_01_52 fig_01_53

  33. fig_01_57 Multiple levels--examples fig_01_57

  34. fig_01_58 fig_01_58

  35. table_01_03 table_01_03

  36. Op code (3) Addr Mode (2) Address (13) M: memory MA: memory address register MD: memory data register IR: instruction register AC: accumulator CF: carry flag IA, IB: index registers (13 bit) PC: program counter Ex 2: Minimal hardware resources  high degree of functionality What should instructions be? M MA IR AC CF MD IA IB PC ABUS BBUS ALU ALU OUTPUT Instruction format: OBUS Functionality: 2's complement add, subtract, multiply, and divide, and, or, not jumps (conditional and unconditional), simple subroutine call and return Interrupts I/O

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