Actel A54SX-A and RTSX-SU Reliability Testing Update

1. Actel A54SX-A and RTSX-SU Reliability Testing Update Antony Wilson, Minal Sawant, and Dan Elftmann

2. S-Antifuses • S-antifuses connect the output track of one logic module to the input track of another logic module • Single S-antifuse nets do not use freeways • No horizontal or vertical freeway connection • Much lower capacitive loading than other types of nets • Much faster edge rates and higher peak operational current Cross Antifuse (“X-antifuses”) Logic Module Logic Module Input Antifuses (“I-antifuses”) Logic Module Logic Module Semi-Direct Antifuses (“S-antifuses”) Single S-antifuse Net Freeway Antifuses (“F-antifuses”)

3. Programming Roadmap (1) • UMC Modified Algorithm (UMA) • UMA will provide low programming current antifuses longer soaking pulses, in order to ensure no weak links • Includes S, B, I and K-antifuses • UMA will be included in Silicon Sculptor II • Version 3.90 (DOS) / 4.53 (Windows) • Shipping since July 2005 • UMA uses the new AFM format • Introduced in Designer 6.1-SP1 • Shipping since March 2005

4. Programming Roadmap (2) • S-Antifuse Loading (SAL) • Adds capacitive loading by connecting a freeway track • Reduces IPEAK in single S-antifuse nets by a minimum of 33% • No measurable increase in routing delay of single S-antifuse nets • Requires design re-compilation • Placement will not change, only routing capacitance is added • Timing changes are minimal • Timing analysis encouraged • AFM checksum changes • SAL Availability • Designer / Libero version 6.2-SP1 • Shipping since August, 2005 Logic Module Logic Module Single S-Antifuse Net Freeway track adds capacitive loading

5. Aerospace Space Qualification • Reliability testing to be done by Aerospace Corporationin Space Qualification • Additionally • Actel donating 80 A54SX72A-PQ208I units to Aerospace Corp. for testing of SAL & UMA in Long Term Life Experiment (LTLE) • Actel donating 80 RTSX72SU-CQ208B units to Aerospace Corp. for testing of SAL & UMA in Long Term Reliability experiment

6. High Single S-Antifuse Design Objective • Create a reliability test vehicle design that approaches, if not achieves, the maximum number of Single S-Antifuses in a ’72 size device • Nets must be capable of being toggled on a Burn In Board (BIB) at a high toggle rate • Delay line time should be ~100 ns (short) to reduce thermal influence on measurement

7. High Single S-Antifuse DesignCombinatorial Circuit(s) • Combinatorial (C-Cells) logic utilization to achieve high S-antifuse count • S-antifuse used in every routing path between c-cells

8. High Single S-Antifuse DesignSequential Circuit(s) • Sequential (R_Cells) logic utilization to achieve high S-antifuse count • S-antifuse is only on nets routed within a super-cluster • Circuit acts like dominoes; CLKB sets up the dominoes and HCLK knocks them down

9. HiSS A54SX72A-PQ208 Antifuse Utilization UMA Algorithm applies to all B, I, S & K antifuses B=> 0 Antifuse between Local Track and input I=> 987 Antifuse between horizontal segment & input S=> 5007 Antifuse between output track & input (semi-direct) K=> 2033 Antifuse between input & horizontal NCLK0 or NCLK1, or QCLK 8027 Total Low Programming Current Antifuses F=> 1029 Antifuse between freeway & output track X=> 1026 Antifuse between horizontal segment & freeway V=> 0 Antifuse between two vertical tracks H=> 0 Antifuse between two horizontal tracks W=> 31 Antifuse between horizontal segment & 2nd freeway on the net (old-style freeway) G=> 0 Antifuse between output track & 2nd, 3rd, & 4th freeway on the net 2086 Total High Programming Current Antifuses 10113 Total Dynamic Antifuses J=> 45116 Antifuse between input & horizontal NVCC or NGND M=> 46 Antifuse for I/O configuration options Q=> 10 Silicon Signature antifuse in silicon signature words T=> 0 Antifuse between output track & input used early in programming sequence to tie off floating output track Y=> 15769 Antifuse between horizontal segment & vertical NVCC or NGND Z=> 9074 Antifuse between freeway & horizontal NVCC or NGND 70015 Total Static Antifuses 80128 Total Antifuses All 5,007 S-Antifuses are Single S-Antifuse nets

10. High S-Antifuse Stress QualificationSX72A-PQ208 UMC 24MHz D1JJT1

11. High S-antifuse Stress QualificationNext Steps • Continue 108 HiSS units w/STD algorithm to 2000 hrs • VCCA = 2.50 V TA = 85ºC • Will add 132 HiSS units w/STD algorithm • VCCA = 2.50 V TA = 85ºC • Continue 108 HiSS units w/UMA algorithm & SAL to 2000 hrs • VCCA = 3.00 V TA = 100ºC

12. NASA Test Based on Shape Factor of Aerospace 72SXAU Long Term Experiment

13. S Antifuse FIT CALC for NASA 32S Test • 0.0091 in 100K Hours = 91 FIT • 5X for 0.2eV • TJ = 150ºC • 10X for Voltage Acceleration • VCCA = 2.75 V • 2X for Utilization • Single S-Antifuse utilization 251 vs. 832 • 5X for Visibility • If delay >10ns no visibility factor • FITs = 91/500 = .182 FIT in 10 Years

14. B-Antifuse within the Device Architecture • The B-Antifuse is driven by the dedicated DB-Inverter in each C-Cell • 4,126 unique functions exist in the RTSX-SU library • 16,879 different configurations • 3,730 of these macro library configurations utilize B-Antifuses • 3,001 Macros have single B-Antifuse configurations • 2,565 have no other option • 337 Can be implemented without the B-Antifuse map string configurations • 99 have a multiple B-Antifuse map string option for macro implementation • None of the 3,730 have a don’t care input available for additional loading

15. B-Antifuse Usage Statistics

16. HiBS • Design Concept • Maximize B-Antifuse utilization using CM8INV macros • Maximize S-Antifuse utilization by routing c-cells in serial chain within supercluster

17. HiBS • Routing within a supercluster to maximize S-Antifuse utilization • Routing technique on a device

18. HiBS A54SX72A-PQ208 Antifuse Utilization B=> 4900 Antifuse between Local Track and input S=> 2248 Antifuse between output track & input(semi-direct) I=> 1755 Antifuse between horizontal segment & input K=> 21 Antifuse between input & horizontal NCLK0 or NCLK1, or QCLK 8924 Low Programming Current Dynamic Antifuses F=> 4024 Antifuse between freeway & output track G=> 0 Antifuse between output track & 2nd, 3rd, & 4th freeway on the net H=> 0 Antifuse between two horizontal tracks V=> 0 Antifuse between two vertical tracks W=> 15 Antifuse between horiz segment & 2nd freeway on the net (old-style freeway) X=> 1774 Antifuse between horizontal segment & freeway 5813 High Programming Current Dynamic Antifuses 14737 Total Dynamic Antifuses J=> 44219 Antifuse between input & horizontal NVCC or NGND M=> 24 Antifuse for I/O configuration options Q=> 11 Silicon Signature afuse in silicon signature words Y=> 15021 Antifuse between horizontal segment & vertical NVCC or NGND Z=> 6095 Antifuse between freeway & horizontal NVCC or NGND 65370 Total Static Antifuses 80107 Total Antifuses UMA Algorithm applies to all B, I, S & K antifuses All 4,900 B-Antifuses are Single B-Antifuse nets

19. High B-Antifuse Stress ExperimentsA54SX72A-PQ208 UMC 24 MHz

20. Aerospace Space QualificationBased on Shape Factor of A54SX72A (UMC)Aerospace Long Term Experiment (ALTE)

21. B-Antifuse FIT CALC for 32S Aerospace Space Qualification • 0.0307 to 0.0458 in 100K Hours = 307 - 458 FIT • 50 – 60% Confidence • 5X for 0.2eV • Tj = 150ºC • 5X for Utilization • Single B-Antifuse utilization 645 vs 3232 • 2.5X for Visibility • 5X < 10ns • 1X > 10ns • FITs = 307 to 458 / 67.5 = 4.6 to 6.8 FIT in 10 Years

22. Aerospace Space Qualification