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Punch-through location in ATLAS SCT sensors

Punch-through location in ATLAS SCT sensors. Outline Introduction Electrical measurements Thermal Imaging Studies Conclusions Appendix. A.Chilingarov, Lancaster University, UK B.Hommels, Cambridge University, UK A.Weidberg, Oxford University, UK. 1. Introduction.

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Punch-through location in ATLAS SCT sensors

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  1. Punch-through location in ATLAS SCT sensors • Outline • Introduction • Electrical measurements • Thermal Imaging Studies • Conclusions • Appendix A.Chilingarov, Lancaster University, UKB.Hommels, Cambridge University, UKA.Weidberg, Oxford University, UK

  2. 1. Introduction • The punch-through protection (PTP) in the p-in-n SCT sensors is more simple than that in the n-in-p Upgrade sensors and therefore should be easier to understand. • On the one hand this understanding is important for predicting the SCT sensors behaviour under heavy flux of particles (e.g. during a beam splash). • On the other hand it may shed a light on the puzzles observed in the PT operation of the Upgrade sensors (e.g. almost identical PT operation of the sensors with and without special PTP structures).

  3. e A Rstr Rb Rdyn In a typical measurement a DC potential, Ustrip, is applied to the strip implant near bias resistor and the resulting current, Istrip, is measured. The slope dUs/dIs gives an effective dynamic resistance, Reff, between the strip and the bias rail. In the above case the Reff consists of the bias resistor, Rb, with Rdyn + Rstr in parallel. Here Rdyn is the dynamic resistance of the 8 mm punch-through gap at the side opposite to the bias resistor (far side). Above the PT onset voltage Rdyn decreases quickly with Ustrip. If the PT develops only at the far side, the strip implant resistance Rstr of ~ 500 kW should limit Reff at Rb||Rstr value of ~ 400kW. Since the PT gap at the bias resistor side (near side) is ~30 mm it was usually assumed that the PT develops mainly at the far side. The quoted gap dimensions are from Hamamatsu (courtesy of Nobu Unno). The photographs made recently at Cambridge confirmed a strong PTP gap asymmetry.

  4. SCT sensor strip Geometry: far side End cap sensor, far side of the strip. Barrel sensor, far side of the strip. All dimensions are in microns.

  5. SCT sensor strip Geometry: near side End cap sensor, near side of the strip. Barrel sensor, near side of the strip. All dimensions are in microns.

  6. However it was long time known that the dynamic resistance in the PT measurements drops well below the expected saturation level of ~400 kW. In this example the results are shown for 7 end-cap sensors of different types. There may be two possible explanation of such a behaviour. Either the strip implant resistance is much lower than the value of ~500 kW given by Hamamatsu (via Nobu Unno) or the PT develops also at the resistor side and with a similar onset voltage. To clarify this situation the dedicated measurements were performed recently with several barrel sensors which in contrast to the end-cap sensors allow the strip implant access at both sides of the strip.

  7. 2. Electrical measurements Lancaster, December 2009 To study the PT at the near and far side of the strip separately the strip edge opposite to that of the test voltage application was grounded. Corresponding curves are labelled as “far (near) only”. For reference purposes a standard measurement with the Ustrip applied at the near side with the far side floating was also made (“near&far” curve). For the Ustrip applied at the far side the initial plateau resistance is at 507 kW level in agreement with the expected implant resistance value. When the Ustrip is applied at the near side the plateau is at 1480 kW (representing Rbias) if the far edge is floating and at 387 kW for the far edge grounded (“near only” case). The latter number is close to 1480 kW || 507 kW. Obviously the PT develops at both edges of the strip.

  8. Lancaster, December 2009 Subtracting the ohmic current Ustrip*Rplateau from the total current allows calculation of the PT current. The results are shown for the same measurement configurations as in the previous slide. Surprisingly the PT onset for the near side alone (~9.5V) is lower than that for the far side alone (~11.5V) in spite of a much larger PT gap at the near side. For the “near&far” case the current follows exactly the pattern of “near only” current up to 11.5V where an additional contribution from the PT at the far side appears. By separate measurements it was proven that the PT current doesn’t “leak” to neighbouring strips but flows directly to the bias rail. The details of these measurements can be found in the Appendix to this talk.

  9. 3. Thermal Imaging Studies Simulation of thermal excess as a result of PTP breakdown (S. Yang, Oxford): Geometry: Silicon plate: 60mm x 60mm x 0.3mm Heat source: 0.02mm x 0.02mm x 0.005mm, -- case 1 0.02mm x 0.02mm x 0.01mm, -- case 2 0.02mm x 0.02mm x 0.02mm, -- case 3 Loading conditions: Heat source total power: 0.001 Watts. Boundary conditions: Applied convection coefficient of 2.5E-5 W/mm^2-C (still air) to the top face of Silicon plate. a: assume all other surfaces are adiabatic boundary condition. b: fixed temperature at other faces at 20 deg C. Results: => Best-case temperature rise: 0.16K

  10. As the expected temperature rise due to PTP breakdown is tiny, the best place one could hope to observe it would be the far end, where the PTP gap is only 8µm. The IR imaging resolution has to match the gap size, as the proximity of metal surfaces will equalize any temperature excess. On the Rbias side, thermal effects originating from the PTP gap will be obfuscated by the Poly-Si layer stacked on top of it. Attempts were made to confirm PTP using sensitive IR imaging equipment (thanks to G. Villani, RAL) , at ~40x increased power dissipation. It was confirmed that measuring such a small thermal excess is a non-trivial affair, however.

  11. Conclusions • In the SCT sensors the punch-through happens at both edges of the strip. Therefore the PT current is not limited by the strip implant resistance of ~500 kW. • Near the bias resistor the PT gap is several times larger than that at the opposite (far) side. Nevertheless the PT onset voltage at the near side is lower than at the far side. It would be very useful to understand the reasons for this. • The PT current doesn’t leak to neighbouring strip but flows directly to the bias rail. • 3. It was found quite difficult to pin-point the PT location with the help of the infra-red camera.

  12. 5. Appendix: PT “leak” study Lancaster, January 2010 The method is based on the interstrip resistance measurement technique. The potential called Vmaster is applied to the implant of the strip 400 and the potential (called Uslave) induced at a neighbour strip is measured. The ratio Rsm=Uslave/Vmaster is a measure of the current leak to the “slave” strip. Four consecutive Vmaster scans from 1 to 23 V were made with the following strips used as the “slaves”: 399 (immediate neighbour), 427, 371, 399 once more. The master I-V curves show the PT above ~10 V.

  13. Lancaster, January 2010 For Vmaster ~20V the Uslave is ~1mV i.e. Rsm~5*10-5. that shows good interstrip isolation. The relation between Uslave and Imaster is in a good approximation linear. The slope is about the same for low Imaster, dominated by a current through the bias resistor, and high Imaster where the PT dominates. This means that the PT current doesn’t leak to the “slave” strip more than the normal ohmic current. The Uslave induced on the immediate neighbour strip 399 doesn’t differ from that induced at the distant strips 427 and 371. This shows that it originates not from the leak between the strips but from a more general link e.g. via bias rail. The necessary parasitic resistance of ~ Uslave/Imaster is ~10W that is small enough to be plausible.

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