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ALICE DAQ future detector readout

ALICE DAQ future detector readout. Filippo Costa ALICE DAQ. October 29, 2012 CERN. Outline. Current status and evolution LS2 upgrade Architectural issues Development process Present R&D activities. Trigger – DAQ – HLT. PDS. Rare/All. CTP. L0, L1a, L2. BUSY. BUSY. LTU. LTU. DDL

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ALICE DAQ future detector readout

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  1. ALICE DAQfuture detectorreadout Filippo Costa ALICE DAQ October 29, 2012 CERN

  2. Outline Current status and evolution LS2 upgrade Architectural issues Development process Present R&D activities Filippo Costa, CERN

  3. Trigger – DAQ – HLT PDS Rare/All CTP L0, L1a, L2 BUSY BUSY LTU LTU DDL H-RORC L0, L1a, L2 HLT Farm TTC TTC FEP FEP FERO FERO FERO FERO Event Fragment Sub-event Event File 10 DDLs 10 D-RORC 10 HLT LDC 120 DDLs 360 DDLs 430 D-RORC 175 Detector LDC D-RORC D-RORC D-RORC D-RORC D-RORC D-RORC LDC LDC LDC LDC LDC Load Bal. Event Building Network (20 GB/s) EDM 75 GDC 30 TDSM GDC TDSM DADQM DSS 60 DA/DQM 18 DSS Storage Network (8GB/s) Archiving on Tapein the ComputingCentre (Meyrin) 75 TDS Filippo Costa, CERN

  4. DDL current status (Oct ‘12) Filippo Costa, CERN

  5. LS2 Online Upgrade ~ 2500 DDL3s10 Gb/s 10 or 40Gb/s DAQ and HLT 2x10 or 40 Gb/s Farm Network Storage Network CLK FLP ITS RORC3 EPN FLP TPC RORC3 FLP TRD RORC3 DataStorage EPN FLP EMCal RORC3 L0 FLP PHOS DataStorage RORC3 EPN FLP TOF RORC3 FLP Muon RORC3 L0L1 EPN FLP FTP RORC3 Trigger Detectors Filippo Costa, CERN

  6. LS2 upgrade requirements (LoI) • The rate for heavy-ion events handled by the online systems up to permanent data storage should be increased up to 50 kHz (with a safety factor of 2) corresponding to roughly two orders of magnitude, compared to the present system. • Data compression will reduce the input peak data throughput of 1 TByte/s to an average recorded data output of 80 GB/s to a local data storage and 12 GB/s to the computing center. Filippo Costa, CERN

  7. Trigger & DAQ logical model LHC Clock LHC Clock Detector Fast Trigger Processor Detector Electronics Digitizers Front-end Pipeline/Buffer Trigger Level 0,1 Decision Readout Buffer Trigger Level 2 Decision Online System Detector Data Link (DDL3) Data compression 1 Cluster finder (RORC3) Distribution of functionsas presented in the LoI Sub-event Buffer First-Level Processor (FLP) Event-Building Network Data compression 2 Event-Building Event-building and Processing Node (EPN) Filippo Costa, CERN

  8. Trigger & DAQ logical model LHC Clock LHC Clock Detector Digitizers Front-end Pipeline/Buffer Trigger Level 0,1 Decision Readout Buffer Trigger Level 2 Decision Data compression 1 Cluster finder Detector Data Link (DDL3) Alternatives scenarios exist: e.g. cluster finder as part ofthe detector readout Sub-event Buffer First-Level Processor (FLP) Event-Building Network Event-Building Data compression 2 (EPN) Filippo Costa, CERN

  9. Development process • Initial requirements in the LoI. • Carry on with functional requirements and R&D in parallel • Refine detectors functional requirements for DCS, TRG, DAQ in view of the detector TDRs (2013) • Online R&D to develop prototypes in view of Online/Offline TDR (2014) • DDL2: • Prototype characterization • Production for the TRD and the HLT • DDL3 • Technology selection • Online dataflow demonstrator • Detector readout, FLP, network, EPN Filippo Costa, CERN

  10. Benefit of the commonality • So far we used a common protocol and hardware (SIU – DDL – RORC) for the read-out of all detectors. • Lots of benefits: • having the same data transmission protocol for all the detectors reduces specific debugging sessions. • It encourages knowledge sharing between the detectors. • It creates the “standard” in a custom protocol. • We are planning to follow the same idea in the future upgrades, using a common protocol for sending data to the DAQ system. Filippo Costa, CERN

  11. DDL SIU evolution Det. Read-Out FPGA Det. Read-Out FPGA SIU IP CORE SIU IP CORE Filippo Costa, CERN

  12. RORC evolution Filippo Costa, CERN

  13. Transition DDL1 to DDL2 + Filippo Costa, CERN

  14. R&D DDL3 Data transmission protocols are under evaluation, for the time being no final decision has been taken yet. Each protocol has different pros and cons, tests started already now, soon to come a reasonable decision. DDL3 Filippo Costa, CERN

  15. UDP Ethernet 10Gb The evaluation for UDP Ethernet data transmission protocol has already started. Preliminary tests have been performed together with RD51 collaboration(Hans MULLER, Alfonso TARAZONA MARTINEZ). A test system has been prepared: • 1 SRU board with a VIRTEX6 , 10 Gb IPOPENCORE. • 1 Machine (DELL server power Edge r 720) with 10 Gb/s port embedded in the motherboard. Continuous readout, no external trigger system, no timeout between 2 packets. Filippo Costa, CERN

  16. UDP Ethernet DDL optical fibre SFP+ 10 Gb/s 10 Gb/s embedded in the motherboard XILINX VIRTEX 6 Filippo Costa, CERN

  17. UDP Ethernet 100 kHz Filippo Costa, CERN

  18. UDP Ethernet (pro/con) Easy to implement in FPGA (IP cores available for 10 Gb/s). Fast and light protocol (no overhead for handshaking). Allow different configurations, point to point or network with routers. Reduce the hardware needed by the detector team to build test system, they can test their readout system using a standard Ethernet port of the PC. Is it rad tool ? We (ALICE DAQ+RD51) are evaluating different solutions. SmartFusion2: XGXS/XAUI Extension (to implement a 10 Gbps (XGMII) Ethernet PHY interface) Not reliable (but software checks can increase the reliability, backpressure algorithm implemented in UDP DATE). High CPU consuming, moving data from the Ethernet port to the memory, but different companies are already addressing the issue, PLDA and Solarflare. IP core license costs for 10 Gb/s can be expensive and not portable outside CERN, but OPENCORE can be a solution for that. Filippo Costa, CERN

  19. TTCrq/rx Det. readout electronics FPGA TTC VHDL All the detectors in ALICE receive the trigger messages through the TTCrx chip or the TTCrqboard. Some of them will integrate the functionalities in the readout electronics. The code will be implemented in the FPGA, so there is no need anymore of the TTCrq boardor TTCrx chip to be installed on each readout card, removing the problem of spare components. Filippo Costa, CERN

  20. Radiation, how to beat it Use of radiation tolerant FPGA: ACTEL(www.actel.com). • Using partial reconfiguration of FPGA • reloading part of the firmware when: • SEU is detected, • periodically CSABA SOOS “SEU effects in FPGA How to deal with them?” http://www.google.it/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&sqi=2&ved=0CEoQFjAD&url=http%3A%2F%2Findico.cern.ch%2FgetFile.py%2Faccess%3FcontribId%3D8%26resId%3D2%26materialId%3Dslides%26confId%3D56796&ei=zeeIUOzUFtCQswaRyIFQ&usg=AFQjCNFjtJxDqKSGVzYv6pD-x-2b4yfD4w Filippo Costa, CERN

  21. Thanks!

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