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Xilinx Alliance Series

Xilinx Alliance Series. Xilinx/Synopsys Powerful High Density Solutions. http://www.xilinx.com/products/alliance.htm. The Synopsys Advantage. Synopsys - Committed to Synthesis Own 90% Synthesis Market 14,000 FPGA design seats Comprehensive Product Offering Synopsys ASIC & FPGA

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Xilinx Alliance Series

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  1. Xilinx Alliance Series Xilinx/Synopsys Powerful High Density Solutions http://www.xilinx.com/products/alliance.htm

  2. The Synopsys Advantage • Synopsys - Committed to Synthesis • Own 90% Synthesis Market • 14,000 FPGA design seats • Comprehensive Product Offering • Synopsys ASIC & FPGA • VIEWlogic System Level & FPGA • LMG Simulation Modeling • QuadMotive Static Timing Analyzer • Path to Higher Level Synthesis Tools • Verification at Every Stage of Design • Post Synthesis, Post P&R, Timing Analysis

  3. The Xilinx Synopsys Advantage • OEM Agreement for FPGA Express • Device support upon introduction • Enhanced Design Performance • Joint development teams • Xilinx specific optimization • Advanced implementation technology • QOR Improvements • Ongoing synthesis benchmark feedback The Key to Success is A Strong Committed Partnership!

  4. FPGA Express

  5. Optimization Technology • General Optimization • Timing Driven Synthesis • Resource Sharing • LUT Based Mapping • Xilinx Specific Optimization • Clock Enable Flip-Flop Mapping • Carry Logic Mapping for arithmetic functions • Automatic Clock Buffer Mapping • Automatic GSR Inferencing • Complex IO Pad Mapping • Slew Rate Control • Pad location assignment

  6. Datapath Synthesis - Module Generation & Mapping • Operators • Adders, subtractors, comparators, counters. • Multipliers • Instantiate using LogiBlox and/or COREgen • RAM • FIFO • Multipliers (pipeline)

  7. State Machine Optimization • Automatic FSM Encoding • One Hot or Binary • User selectable option • Coding Style Template • Templates in On-Line Help • Enumerated type in VHDL • parameter in Verilog

  8. Timing Driven Design • 1.Timing Characterization • Logic Level Optimization • Clock Waveforms • Builds Table of all Clock Nets • You can Specifies Clock Waveforms • Paths Group • Identifies all clock groups • Calculates ConstraintsBased on Clock Waveforms • You Can Override theseConstraints, e.g. multi-cycle

  9. Timing Driven Design • 2.I/O Port Control • Builds a Table of All I/O Ports • You can Specify: • Pin Location • Pad Type (slew, resistance…) • Input / Output Delay • IO Register Mapping • Specify Pull-Up on IOs • Hierarchy Control • Displays Design Hierarchy • Preserve Hierarchy • Resource Sharing 3.

  10. Integration, Foundation ExpressEase-Of-Use • Timing Constraints • Single Entry • Propagation to place & route • via timespec today • via NCF in F1.5 • Integration of synthesis and place & route • Forward annotation of constraints • Error Navigation to source within Express

  11. Xilinx Specific Features • FPGA Express Passes the Timing Constraints to the Netlist for Xilinx’ P&R Using TIMESPEC • Timespecs symbols placed in top level XNF • via NCF in F1.5 Input Setup Clock-to-Out Reg-to-Reg SYM, TS0, TIMESPEC, TS0=from:pads:to:tgrp_0_DFF=20ns, LIBVER=2.0.0 END SYM, TS1, TIMESPEC, TS1=from:tgrp_0_DFF:to:pads=20ns, LIBVER=2.0.0 END SYM, TS2, TIMESPEC, TS2=from:tgrp_0_DFF:to:tgrp_0_ DFF=10ns, LIBVER=2.0.0 END

  12. Xilinx Specific Features • FPGA Express Automatically Infers Global [Asynchronous] Set/Reset Line • Initializes Each Register to Either Set or Reset • Dedicated Distribution Network • Reduces Routing Congestion • Reset signal must source all FF’s

  13. High Density Methodology • Advanced Hierarchy Management • Boundary Optimization • Ability to preserve/eliminate hierarchy boundary • Automatic uniquification • Complete Design or Module Level Control • Built for Top-Down • Incremental Design • Joint Development in Progress

  14. Synopsys FPGA Compiler

  15. High Density Methodology • Advanced Hierarchy Management • Boundary Optimization • Ability to preserve/eliminate hierarchy boundary • Automatic uniquification • Complete Design or Module Level Control • Built for Top-Down • Incremental Design • Joint Development in Progress

  16. Optimization Technology • Generic Optimization • Timing Driven Synthesis • LUT Based Mapping • Resource Sharing • Xilinx Specific Optimization • Clock Enable Flip-Flop Mapping • Carry Logic Mapping for arithmetic functions • Automatic Clock Buffer Mapping • Limited to input ports • Complex IO Pad Mapping • Slew Rate Control • Pad location assignment

  17. Datapath SynthesisModule Generation & Mapping • DesignWare Library • Counters, adders, subtractors, comparators • Multipliers Synopsys DW only • Instantiate using LogiBlox and/or COREgen • RAM • FIFO • Multipliers

  18. State Machine Optimization • State Machine Compiler • FSM Extraction • < 20 states • Explicitly Encode • > 20 states and more • Strengths and limitations • State Machine extraction at netlist level • Expert User

  19. State Machine Optimization • State Machine Compiler • FSM Extraction • < 20 states • Explicitly Encode • > 20 states and more • Strengths and limitations • State Machine extraction at netlist level • Expert User

  20. Xilinx Specific Features • Passing Constraints to Place and Route • dc2ncf • Design Recommendations • Do not Overconstrain design • Flatten Design for translation

  21. Timing Driven Design • Design Constraints • clocks • input setup • clock-to-out • multi-cycle path • Optimization Directives • Boundary Optimization • Mapping Effort • re-timing using balance_registers (for XC4000) • Scripting Capability • dc_shell, ASIC migration

  22. High Density Methodology • Boundary Optimization • Maintain large hierarchical blocks • Group • Based on critical path • Ungroup • Enable dc2ncf • Faster ngdbuild runtimes • Fanout Control • Module Level Control

  23. A B C COMBO LOGIC B COMBO LOGIC C COMBO LOGIC A REG A REG C Bad CLK CLK A C REG C REG A COMBO LOGIC A & B & C Good CLK CLK A C Best REGA REG C COMBO LOGIC A & B & C CLK CLK Recommended Design Technique • Registers at output of hierarchical boundary

  24. Features : • Complete DCScript Compatibility • Timing Driven Design • Features: • Highest Quality of Results • Fast Run times • Easy-to-use GUIs FPGA Compiler IITwo Tools in a Single Package FPGA Compiler II- Phase 1 FPGA Compiler PLUS FPGA Express PC, UNIX Source code is 100% compatible

  25. FPGA Express Push-button user interface, Easy-to-Use design constraint entry, Optimized for FPGAs FPGA Compiler Full Design Compiler compatibility, Complete ASIC FPGA flow support FPGA Compiler II provides Flexibility The freedom to choose the right tool when you need it!

  26. FPGA Compiler II Road Map FPGA Compiler II FPGA Compiler II • FPGA Express • Technology: • DC Compatibility • Design Constraint Entry • Seamless ASIC Migration • Incremental Synthesis FPGA Compiler FPGA Compiler FPGA Express 1997 February 1998 future

  27. Consider FPGA Compiler II & Xilinx • Push Button Algorithms • Automatic IO pad mapping • Built in module generation • Automatic Global Signal Mapping • Resource Sharing • Full Control to Specify Design Performance • Timing constraints • Hierarchy structure • Device Buffers • All Constraints Passed to Implementation Tools! Best Results Quickly and Easily!

  28. HDL Compiler VHDL Compiler FPGA Express Technology Delivers Taking FPGA Synthesis to the Next Step • New Generation Synthesis Technology for FPGAs improving QOR and utilization • Push Button Design Flow for intuitive ease-of-use • Synopsys-supplied libraries for highest QOR • Advanced device information providing synthesis support at device introduction When benchmarked - Hands Down WINNER over the Free stuff!

  29. FPGACompiler II Delivers The First Quality FPGA Synthesis Tool • Higher device efficiency with fine tuned algorithms for Xilinx architectures (LUT optimization) • Enhanced device utilization with automatic carry chain and cascade logic mapping • Ease of use with intuitive graphical user interface • ASIC compatibility with seamless flow from FPGA to ASIC

  30. FPGA Verification & Debugging Logic Modeling • Focus on design and system verification rather than simulation details • Debug functionality and timing quickly • Quickly identify root of logic/timing errors and reprogram model during simulation • Simulate • Modify your design • Reprogram SmartModel • Continue to simulate with modified design • Quick incremental design changes speeding up design turns • Support for 3K, 4K, Spartan, 5K, and XC9500 Design Flow design entry synthesis • Modify design if necessary. Repeat. Xilinx Implementation Tools Xilinx Netlist SmartModel • Program model • Simulate FPGA • in system Program device System Design

  31. 1 A J F H B PLdebug E 1 C G K I 0 D 12 I_Bus 5D0E I_Addr 204F38 FPGA OE_Ctrl 0 S_Count 1011 SM Windows Visual SmartBrowser SmartModel FPGA/CPLD PLdebug, SmartModel Windows, Visual SmartBrowser Significantly reduce debug time for Xilinx FPGA/CPLD designs Verification FlowLogic Modeling

  32. Summary • Overview of current features • Mapping Control • Ability to direct logic to HMAP and FMAP • Single Constraint Entry and Propagation to P&R • Preserve Hierarchy • Faster runtime than FC (~10x) • Module Generation • Future Development • Schematic View and cross-probe to source • Scripting capability • Incremental Synthesis

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