Thermal Via Placement in 3D ICs

1. Thermal Via Placement in 3D ICs Brent Goplen, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota

2. Overview • Introduction • Simplified Example • Formulation • Results • Conclusions

3. Layer 5 Layer 4 Layer 3 Layer 2 Layer 1 Bulk Substrate 3D IC Using Wafer Bonding Detailed view Generalized view SOI wafers with bulk substrate removed Inter-layer bonds 1mm Bulk wafer Metal level of wafer 1 10mm 500mm Device level 1 Adapted from [Das et al., ISVLSI, 2003]

4. 3D Global Net Distributions 1400 1200 4 Strata 2 Strata 1000 1 Stratum 800 Net Density (#/mm) 600 400 200 0 0 5 10 15 20 25 30 35 Length (mm) from Intel Improvements and Obstacles of 3D ICs Benefits • Reduced wirelength • Lower power per transistor • Decreased delay • Higher packing densities • Smaller chip areas Obstacles • Processing technology • Thermal issues • Higher power densities • Increased thickness • Insulating materials • 3D design tools [Joyner, Zarkesh-Ha and Meindl, ASIC/SOC ’01]

5. Rearrange heat sources • Manually fix hot spots • Thermal placement • Improved heat sinking • Improved packaging • More efficient heat removal • Improved thermal conduits • Internal heat sinking • Thermal via placement • Minimize power usage • Low-power design • Minimize wirelength Methods of Mitigating Thermal Problems

6. Thermal vias Electrically isolated vias Used for heat conduction Thermal via regions Only region where thermal vias are allowed Predictable obstacle for routing Variable density of thermal vias Substrate Thermal Via Thermal Via Regions

7. Thermal Via Region Inter-layer elements Row Region Layer elements Inter-Row Region Standard cells (heat sources) Bulk substrate elements Thermal Vias in 3D ICs

8. Benefits and Challenges • Benefits • Reduced temperatures • Uses existing via fabrication • Benefits 3D ICs more • Challenges • Creates obstacles to routing • Where to put them? • CAD tools needed

9. Overview • Introduction • Simplified Example • Formulation • Results • Conclusions

10. Thermal Via Regions { Heat Sources (standard cells) Layers and inter-layers Bulk Substrate Simplified Example

11. Simplified Example

12. 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W Simplified Example 1 2 3 4 5 6 10W 7 8 9 10

13. 10oC/W 10oC/W 65oC 70oC 65oC 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 59oC 81oC 59oC 10oC/W 10oC/W 10oC/W 10oC/W 10oC/W 32oC 36oC 32oC 10oC/W 10oC/W 10oC/W 0oC Simplified Example 10W

14. Simplified Example 65oC 70oC 65oC 6oC 6oC High Temps 10oC/W 10oC/W 59oC 81oC 59oC 10W 27oC 27oC High temp drop 10oC/W 10oC/W 32oC 36oC 32oC 0oC

15. 67 60 60 60 1 1 Simplified Example 65oC 70oC 65oC 10oC/W 10oC/W 60 59oC 81oC 59oC 32oC 36oC 32oC 0oC

16. 44 51 44 64 34 34 37 1 1 Simplified Example 65oC 70oC 65oC Use thermal gradient not temperature! 37 59oC 81oC 59oC 10oC/W 10oC/W 33 32oC 36oC 32oC 0oC

17. High Temperatures Place Thermal Vias

18. High Thermal Gradients Place Thermal Vias

19. Thermal Via Region • Impractical to place thermal vias individually • Use arrangement of thermal vias instead • Gives thermal via density value • Changes the effective thermal conductivity High Thermal Via Density High Effective Thermal Conductivities

20. High Thermal Gradients High Thermal Via Density High Thermal Conductivity

21. Old Temperatures Thermal Gradients Thermal Conductivities New Temperatures

22. Initial Temperatures Thermal Gradients Thermal Conductivities New Temperatures Thermal Via Densities

23. P K ∆T Mathematical Formulation • Heat transfer within an element (region) • K∆T=P • Assume P doesn’t change between iterations • Knew∆Tnew = Kold∆Told • Knew= Kold(∆Told / ∆Tnew) • Using the thermal gradient, g = ∆T/d, • Knew= Kold(gold / gnew) • Let gnew slowly approach an ideal value, gideal • gnew = gideal(gold / gideal)α, 0 ≤ α≤ 1 • Knew= Kold(gold / gideal)1-α • Update gideal using maximum temperature • gideal= gideal(Tmaxideal / Tmax)

24. SET K’s TO MINIMUM AND CALCULATE THERMAL PROFILE CALCULATE THERMAL PROFILE FOR EACH THERMAL VIA REGION UPDATE Kz= Kz (g / gideal)1-α UPDATE m and Klateral Main loop UPDATE gideal = gidealTmaxideal/Tmax CONVERGED? NO YES DONE Thermal Via Placement Algorithm GIVEN IDEAL MAXIMUM TEMPERATURE: Tmaxideal

25. Thermal Conductivities of Thermal Via Regions

26. Range of Temperature Values • Midrange thermal via densities produce • 47.1% lower maximum temperatures • 28.3% lower average temperatures

27. Range of Temperature Values • Midrange thermal via densities produce • 47.1% lower maximum temperatures • 28.3% lower average temperatures

28. Results • Same maximum temperatures as with midrange via densities • 1.8% higher average temperatures • 11.9% thermal via density in thermal via regions (1.2% in chip) • 50.3% lower than the midrange value

29. Results • Same maximum temperatures as with midrange via densities • 1.8% higher average temperatures • 11.9% thermal via density in thermal via regions (1.2% in chip) • 50.3% lower than the midrange value

30. Before Thermal Via Placement

31. After Thermal Via Placement

32. Conclusions • Thermal vias have a greater effect in 3D ICs • Thermal via regions provide regularity • Efficient iterative method • Uses thermal gradients to adjust thermal conductivities • Ideal maximum temperature • Use lowered value as an objective • Minimizes use of thermal vias • Vias are put where they make the most impact • Reduces thermal resistance on heat conduction paths