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Commissioning of the powering interlock system for superconducting circuits

Commissioning of the powering interlock system for superconducting circuits. Markus Zerlauth, AB-CO-IN for the interlock team. Outline. Powering and protection of superconducting magnets for the LHC Architecture and hardware to be commissioned Documentation of commissioning steps

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Commissioning of the powering interlock system for superconducting circuits

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  1. Commissioning of the powering interlock system for superconducting circuits Markus Zerlauth, AB-CO-IN for the interlock team

  2. Outline • Powering and protection of superconducting magnets for the LHC • Architecture and hardware to be commissioned • Documentation of commissioning steps • The different hardware commissioning activities IST:PIC, HCA:SC, HCA:PIC1, HCA:PIC2 • Automated procedures for interlock commissioning • Open issues, conclusions and outlook

  3. Magnet powering of superconducting magnets in the LHC Protection of ~ 150 nc magnets Protection of ~1600 electrical circuits with 10 000 sc magnets + Protection of ~ 800 nc magnets in SPS extractions lines & CNGS Talk of R. Harrison • Other than the interlocks for normal conducting magnets, the Powering Interlock Controllers for superconducting magnets (PIC) will only be present in LHC

  4. The powering interlock system to be commissioned • Common PVSS application • 36 powering interlock controllers • One controller per powering subsector (two for an arc) • In between 8-45 electrical circuits protected by one controller Interlock Rack for an Arc Interlock Rack for an Inner Triplet Interlock Rack for a Matching Section

  5. What do we have to commission? LHC Ref DB PVSS Operator Console In the Field Control Room or CCC • Functionality of the PLC Program • Integrity of hardwired protection signals >2300 fail safe current loops with PCs, QPS, AUG, UPS, BIC • Signal mapping and PVSS functionality • Supervision links in between systems • Loading and transfer of configuration files Ethernet Technical Network PLC in non-radiation area Profibus Remote I/O close to clients PC_PERMIT QPS Power Converter CIRCUIT_QUENCH PC_FAST_ABORT POWERING_FAILURE DISCHARGE_ REQUEST PC_DISCHARGE_ REQUEST

  6. Individual System Tests of Powering Interlock Controller 300 K Test of power converters connected to the DC cables in short circuit, including controls for powering, ramp, monitoring Individual System Tests of the Quench Protection and Energy Extraction Systems 90 K Electrical Quality Assurance 1.9 K Interlock tests of a powering subsector prior and after connection of the power cables to the DFB leads Documentation: superconducting electrical circuits LHC-CI-TP-0001 LHC-R-HCP-0001 LHC-DE-TP-0001 LHC-DQ-TP-0001 Power Converters not connected to Magnets LHC-D-HCP-0005 Post-Mortem System tests LHC-D-HCP-0002 LHC-DFL-HCP-0001 LHC-D-HCP-0001 connexion of power cables to current leads Commissioning of the electrical circuits one by one or in groups at low, intermediate and nominal currents Power Converters connected to Magnets LHC-D-HCP-0006 LHC-D-HCP-0003 Commissioning of all the electrical circuits of the sector powered in unison to nominal current with nominal ramp rates

  7. Initial system state and Individual System Tests IST:PIC • Prior and after installation of a powering interlock controller, the full system functionality is validated in stand-alone mode using a test-system and dedicated VB software • Surface tests will include • PVSS Interface for this instance of interlock controller • Configuration files for PVSS and the PLC • PLC functionality • Hardwired protection signals, emulated via test system • Remote system monitoring • Individual system tests in the tunnel • Basic PVSS functionalities with local connection • PLC functionality • Hardwired protection signals local Ethernet connection INTERLOCK CONTROLLER TESTSYSTEM Duration of IST: 2-4 days / system

  8. Support during PC short circuit tests HCA:SC • The powering interlock system needs to be operational for the main bending and quadrupole circuits (only 13kA) already during the PC short circuit tests • Reason: Transmission of circuit discharge request to the energy extraction systems and the power converter (different from 600A) • Interlock cables, QPS equipment and interlocks for those circuits are required • Tests could be done manually or using automated procedures Power Permit Internal failures / Ground Fault Cooling Failures Power Converter Powering Interlock Controller Duration of HCA:SC: 2 days for each even arc side QPS HTS Current Leads Magnet 1 Magnet 2 DFB

  9. Interlock commissioning HCA:PIC1 and HCA:PIC2 • Upon completion of PC short circuit tests, the remaining interlock cables will be connected • All systems have to be operational and the powering subsector has to be cold • All possible states and failure scenarios are tested followingwell defined procedures (LHC-D-HCP-0002) Gateway(s) PVSS Supervision PVSS Supervision Supervision Applications WorldFIP ETHERNET PROFIBUS DB CMW Gateway PC_PERMIT QPS Power Converter PIC PC_FAST_ABORT CIRCUIT_QUENCH HW Level POWERING_FAILURE DISCHARGE_ REQUEST PC_DISCHARGE_ REQUEST Duration of PIC1: 7-14 days Duration of PIC2: 1-2 days

  10. Example of the transmission of the quench signal of ONE SINGLE CIRCUIT Automated Test Procedures (Sequencer) Sequencer PVSS-CMW Interface PVSS-CMW Interface CMW Gateway(s) PVSS Supervision PVSS Supervision Supervision Applications ETHERNET PROFIBUS DB WorldFIP CMW Gateway PC_PERMIT QPS Power Converter PIC PC_FAST_ABORT CIRCUIT_QUENCH HW Level Action: Initialize all systems, unlatch PC and verify that no green light for powering • Between 10 and 20 actions/verifications to be performed on the different supervision applications for the commissioning of each protection signal • Around 2300 hardwired signals to be commissioned • Automated procedures/Sequencer to interact with the 3 systems Action: Give green light for powering Action: Verify the reception of PC_PERMIT for this converter only Action: Ramp up to standby current (only for HCA:PIC2) Action: Simulate a quench signal for the circuit via the quench protection system Action: Verify the reception in the PIC and the converterfor this circuit Action: Verify the shut-down of the converter and the removal of the PC_PERMIT Action: Re-initialize and repeat the request via the PIC

  11. The sequencer for PC short circuits tests and interlock commissioning • To guarantee an efficient commissioning, automated procedures are being developed (Software Applications for Commissioning of Electrical Circuits) • Sequencer in development, communicating via CMW with all involved systems • Currently PC short circuit tests and Interlock tests available • Not all interfaces ready -> Simulation of PIC and QPS • Final validation of functionality during HWC of LSS8 (manual commissioning and sequencer in parallel) • Prototype demo: http://slwww.cern.ch/~pcrops/releaseinfo/pcropsdist/macsy/macsy-view-lhchwc/PRO/

  12. Commissioning activities for the powering interlock • One team performing IST for interlock controllers in the two sectors and providing the support for the short circuit tests • Four teams for the HCA activities PIC1 and PIC2 and power tests • To staff these 5 required teams -> Five additional people for PIC activities All activities In parallel More ‘Relaxed’ time, used for training of personnel Validation of commissioning procedures & tools

  13. Requirements and assumptions for the PIC commissioning • Each instance of powering interlock controller has to be tested to 100% of it’s functionality, in case of problems -> replacement of hardware and retesting • Experience from debugging in previous sectors will speed up later commissioning, however there is no compromise for the applied procedures • Summary session of the Machine Protection Review: Commission of necessity involves a large amount of equipment failure/repair and associated downtime. It is an inherently risky time. Additional care must be taken to avoid ‘shortcuts’. Responsibilities must be well defined • Additional tests that will be performed in the first sector: • Reaction times of the interlock chains (especially RB circuit with EE on either side) • BIC interface (although commissioned at a later stage) • EMC observations and endurance tests (already lab-tested) • Post Mortem Interface (history buffer of the PLC available through supervision) • Validation of automated procedures in LSS8 • Training of personnel

  14. Conclusions and Outlook • To maintain the present commissioning schedule we rely on the automated procedures • PVSS-CMW interface to be finished • Mapping to the three main supervision applications to be done and tested • Validation of procedures in LSS8 (4 weeks?, can start as soon as all systems and their controls are operational) • Commissioning steps and procedures are well definedand documented (HCWG, SACEC) and will be validated in LSS8 • No specific risk for personnel safety as tests are performed at zero or standby current • Communication in between the involved groups is excellent, few dependencies on other systems during commissioning are well understood

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