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Virtual Memory

Explore the concept of virtual memory, multilevel page tables, and memory mapping in the Pentium/Linux memory system. Learn about address translation and suggested reading.

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Virtual Memory

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  1. Virtual Memory

  2. Outline • Multilevel page tables • Different points of view • Pentium/Linux Memory System • Memory Mapping • Suggested reading: 10.6, 10.3, 10.7, 10.8

  3. 10.6 Address Translation 10.6.3 Multi Level Page Tables

  4. Multi-Level Page Tables • Given: • 4KB (212) page size • 32-bit address space • 4-byte PTE • Problem: • Would need a 4 MB page table! • 220 *4 bytes

  5. Level 2 Tables Level 1 Table ... Multi-Level Page Tables • Common solution • multi-level page tables • e.g., 2-level table (P6) • Level 1 table: 1024 entries, each of which points to a Level 2 page table. • Level 2 table: 1024 entries, each of which points to a page

  6. Multi-Level Page Tables Figure 10.18 P710

  7. Multi-Level Page Tables Figure 10.19 P711

  8. Page 15 PT 3 Page 14 Page 13 Page Directory Page 12 Page 11 P=1, M=1 P=1, M=1 P=0, M=1 P=1, M=1 • • • • PT 2 Page 10 P=0, M=0 P=0, M=1 P=0, M=0 P=1, M=1 • • • • P=0, M=0 P=0, M=0 P=1, M=1 P=1, M=1 • • • • Page 9 P=0, M=1 P=0, M=1 P=0, M=0 P=0, M=1 • • • • Page 8 PT 0 Page 7 Page 6 Page 5 Mem Addr Page 4 Page 3 Disk Addr Page 2 In Mem Page 1 On Disk Page 0 Unmapped Representation of Virtual Address Space • Simplified Example • 16 page virtual address space • Flags • P: Is entry in physical memory? • M: Has this part of VA space been mapped?

  9. 10.4 VM as a Tool for Memory Management

  10. A Tool for Memory Management • Separate virtual address space • Each process has its own virtual address space • Simplify linking, sharing, loading, and memory allocation

  11. 0 Physical Address Space (DRAM) Address Translation Virtual Address Space for Process 1: 0 VP 1 PP 2 VP 2 ... N-1 (e.g., read/only library code) PP 7 Virtual Address Space for Process 2: 0 VP 1 PP 10 VP 2 ... M-1 N-1 A Tool for Memory Management

  12. memory invisible to user code kernel virtual memory stack %esp Memory mapped region forshared libraries Linux/x86 process memory image the “brk” ptr runtime heap (via malloc) uninitialized data (.bss) initialized data (.data) program text (.text) forbidden A Tool for Memory Management Figure 10.10 P702

  13. 10.5 VM as a Tool for Memory Protection

  14. A Tool for Memory Protection • Page table entry contains access rights information • hardware enforces this protection (trap into OS if violation occurs)

  15. Page Tables Memory Read? Write? Physical Addr VP 0: VP 0: 0: Yes No PP 9 1: VP 1: VP 1: Process i: Yes Yes PP 4 VP 2: VP 2: No No XXXXXXX • • • • • • • • • Read? Write? Physical Addr Yes Yes PP 6 Process j: Yes No PP 9 N-1: No No XXXXXXX • • • • • • • • • A Tool for Memory Protection

  16. A Tool for Memory Protection Figure 10.11 P704

  17. 10.7 Case Study: The Pentium/Linux Memory System

  18. P6 Memory System • 32 bit address space • 4 KB page size • L1, L2, and TLBs • 4-way set associative • inst TLB • 32 entries • 8 sets • data TLB • 64 entries • 16 sets • L1 i-cache and d-cache • 16 KB • 32 B line size • 128 sets • L2 cache • unified • 128 KB -- 2 MB • 32 B line size DRAM external system bus (e.g. PCI) 2 L2 cache 3 1 cache bus bus interface unit inst TLB 1) data TLB 2) 3) instruction fetch unit L1 i-cache L1 d-cache 4) processor package Figure 10.22 P716

  19. 10.7.1 Pentium Address Translation

  20. CPU 32 L2 and DRAM result 20 12 virtual address (VA) VPN VPO L1 miss L1 hit 16 4 TLBT TLBI L1 (128 sets, 4 lines/set) TLB hit TLB miss ... ... TLB (16 sets, 4 entries/set) 10 10 VPN1 VPN2 20 7 5 20 12 CT CI CO PPN PPO physical address (PA) PDE PTE Page tables PDBR P6 Address Translation Figure 10.23 P717

  21. P6 Page Table Up to 1024 page tables • Page directory • 1024 4-byte page directory entries (PDEs) that point to page tables • one page directory per process. • page directory must be in memory when its process is running • always pointed to by PDBR • Page tables: • 1024 4-byte page table entries (PTEs) that point to pages. • page tables can be paged in and out. 1024 PTEs page directory ... 1024 PDEs 1024 PTEs ... 1024 PTEs Figure 10.24 P718

  22. P6 page directory entry (PDE) 31 12 11 9 8 7 6 5 4 3 2 1 0 Page table physical base addr Avail G PS A CD WT U/S R/W P=1 Page table physical base address: 20 most significant bits of physical page table address (forces page tables to be 4KB aligned) Avail: available for system programmers G: global page (don’t evict from TLB on task switch) PS: page size 4K (0) or 4M (1) A: accessed (set by MMU on reads and writes, cleared by software) CD: cache disabled (1) or enabled (0) WT: write-through or write-back cache policy for this page table U/S: user or supervisor mode access R/W: read-only or read-write access P: page table is present in memory (1) or not (0) Figure 10.25 (a) P719 31 1 0 Available for OS (page table location in secondary storage) P=0 evict: 驱逐

  23. P6 page table entry (PTE) 31 12 11 9 8 7 6 5 4 3 2 1 0 Page physical base address Avail G 0 D A CD WT U/S R/W P=1 Page base address: 20 most significant bits of physical page address (forces pages to be 4 KB aligned) Avail: available for system programmers G: global page (don’t evict from TLB on task switch) D: dirty (set by MMU on writes) A: accessed (set by MMU on reads and writes) CD: cache disabled or enabled WT: write-through or write-back cache policy for this page U/S: user/supervisor R/W: read/write P: page is present in physical memory (1) or not (0) Figure 10.25 (b) P719 31 1 0 Available for OS (page location in secondary storage) P=0

  24. Page tables Translation 10 10 12 Virtual address VPN1 VPN2 VPO word offset into page directory word offset into page table word offset into physical and virtual page page directory page table physical address of page base (if P=1) PTE PDE PDBR physical address of page table base (if P=1) physical address of page directory 20 12 Physical address PPN PPO Figure 10.26 P720

  25. CPU 32 L2 andDRAM result 20 12 virtual address (VA) VPN VPO L1 miss L1 hit 16 4 TLBT TLBI L1 (128 sets, 4 lines/set) TLB hit TLB miss ... ... TLB (16 sets, 4 entries/set) 10 10 VPN1 VPN2 20 7 5 20 12 CT CI CO PPN PPO physical address (PA) PDE PTE Page tables PDBR P6 TLB translation Figure 10.27 P720

  26. 32 16 1 1 PDE/PTE Tag PD V set 0 entry entry entry entry set 1 entry entry entry entry set 2 entry entry entry entry ... set 15 entry entry entry entry P6 TLB • TLB entry (not all documented, so this is speculative): • V: indicates a valid (1) or invalid (0) TLB entry • PD: is this entry a PDE (1) or a PTE (0)? • tag: disambiguates entries cached in the same set • PDE/PTE: page directory or page table entry • Structure of the data TLB: • 16 sets, 4 entries/set

  27. CPU virtual address 20 12 VPN VPO 16 4 TLBT TLBI 1 2 TLB hit TLB miss PDE PTE 3 ... 20 12 PPN PPO physical address page table translation 4 Translating with the P6 TLB P720 1. Partition VPN into TLBT and TLBI. 2. Is the PTE for VPN cached in set TLBI? 3. Yes: then build physical address. 4. No: then read PTE (and PDE if not cached) from memory and build physical address.

  28. CPU 32 L2 andDRAM result 20 12 virtual address (VA) VPN VPO L1 miss L1 hit 16 4 TLBT TLBI L1 (128 sets, 4 lines/set) TLB hit TLB miss ... ... TLB (16 sets, 4 entries/set) 10 10 VPN1 VPN2 20 7 5 20 12 CT CI CO PPN PPO physical address (PA) PDE PTE Page tables PDBR P6 page table translation

  29. Translating with the P6 page tables (case 1/1) • Case 1/1: page table and page present. • MMU Action: • MMU build physical address and fetch data word. • OS action • none 20 12 VPN VPO 20 12 VPN1 VPN2 PPN PPO Mem PDE p=1 PTE p=1 data PDBR Data page Page directory Page table Disk

  30. Translating with the P6 page tables (case 1/0) • Case 1/0: page table present but page missing. • MMU Action: • page fault exception • handler receives the following args: • VA that caused fault • fault caused by non-present page or page-level protection violation • read/write • user/supervisor 20 12 VPN VPO VPN1 VPN2 Mem PDE p=1 PTE p=0 PDBR Page directory Page table data Disk Data page

  31. Translating with the P6 page tables (case 1/0, cont) • OS Action: • Check for a legal virtual address. • Read PTE through PDE. • Find free physical page (swapping out current page if necessary) • Read virtual page from disk and copy to virtual page • Restart faulting instruction by returning from exception handler. 20 12 VPN VPO 20 12 VPN1 VPN2 PPN PPO Mem PDE p=1 PTE p=1 data PDBR Data page Page directory Page table Disk

  32. Translating with the P6 page tables (case 0/1) • Case 0/1: page table missing but page present. • Introduces consistency issue. • potentially every page out requires update of disk page table. • Linux disallows this • if a page table is swapped out, then swap out its data pages too. 20 12 VPN VPO VPN1 VPN2 Mem PDE p=0 data PDBR Data page Page directory PTE p=1 Disk Page table

  33. Translating with the P6 page tables (case 0/0) • Case 0/0: page table and page missing. • MMU Action: • page fault exception 20 12 VPN VPO VPN1 VPN2 Mem PDE p=0 PDBR Page directory PTE p=0 data Disk Page table Data page

  34. Translating with the P6 page tables (case 0/0, cont) • OS action: • swap in page table. • restart faulting instruction by returning from handler. • Like case 0/1 from here on. 20 12 VPN VPO VPN1 VPN2 Mem PDE p=1 PTE p=0 PDBR Page table Page directory data Disk Data page

  35. CPU 32 L2 andDRAM result 20 12 virtual address (VA) VPN VPO L1 miss L1 hit 16 4 TLBT TLBI L1 (128 sets, 4 lines/set) TLB hit TLB miss ... ... TLB (16 sets, 4 entries/set) 10 10 VPN1 VPN2 20 7 5 20 12 CT CI CO PPN PPO physical address (PA) PDE PTE Page tables PDBR P6 L1 cache access

  36. 32 L2 and DRAM data L1 miss L1 hit L1 (128 sets, 4 lines/set) ... 20 7 5 CT CI CO physical address (PA) L1 cache access • Partition physical address into CO, CI, and CT. • Use CT to determine if line containing word at address PA is cached in set CI. • If no: check L2. • If yes: extract word at byte offset CO and return to processor.

  37. Tag Check 20 7 5 CT CI CO Physical address (PA) PPN PPO Addr. Trans. No Change CI virtual address (VA) VPN VPO 20 12 Speeding Up L1 Access • Observation • Bits that determine CI identical in virtual and physical address • Can index into cache while address translation being performed • Then check with CT from physical address • “Virtually indexed, physically tagged”

  38. Linux Virtual Memory System kernel  virtual  memory process-specific data structures (page tables, task and mm structs) physical memory same for each process kernel code/data/stack 0xc0000000 stack %esp process  virtual  memory Memory mapped region for shared libraries 0x40000000 brk runtime heap (via malloc) uninitialized data (.bss) initialized data (.data) program text (.text) 0x08048000 forbidden 0 Figure 10.28 P721

  39. process virtual memory vm_area_struct task_struct mm_struct vm_end vm_start mm pgd vm_prot vm_flags mmap shared libraries vm_next 0x40000000 vm_end vm_start data vm_prot vm_flags 0x0804a020 text vm_next vm_end vm_start 0x08048000 vm_prot vm_flags 0 vm_next Linux organizes VM as a collection of “areas” • pgd: • page directory address • vm_prot: • read/write permissions for this area • vm_flags • shared with other processes or private to this process Figure 10.29 P722

  40. process virtual memory vm_area_struct vm_end vm_end vm_end vm_start vm_start vm_start r/o r/w r/o shared libraries vm_next vm_next vm_next 1 read 3 data read 2 text write 0 Linux page fault handling • Is the VA legal? • i.e. is it in an area defined by a vm_area_struct? • if not then signal segmentation violation (e.g. (1)) • Is the operation legal? • i.e., can the process read/write this area? • if not then signal protection violation (e.g., (2)) • If OK, handle fault • e.g., (3) Figure 10.30 P723

  41. 10.8 Memory Mapping

  42. Memory mapping • Creation of new VM area done via “memory mapping” • create new vm_area_struct and page tables for area • area can be backed by (i.e., get its initial values from) : • regular file on disk (e.g., an executable object file) • initial page bytes come from a section of a file • nothing (e.g., bss) • initial page bytes are zeros • dirty pages are swapped back and forth between a special swap file.

  43. Memory mapping • Key point: no virtual pages are copied into physical memory until they are referenced! • known as “demand paging” • crucial for time and space efficiency Crucial:至关重要的

  44. 10.8.1 Shared Objects Revisited

  45. Shared Object P725 • shared object • An object which is mapped into an area of virtual memory of a process • Any writes that the process makes to that area are visible to any other processes that have also mapped the shared object into their virtual memory • The changes are also reflected in the original object on disk. • shared area • A virtual memory area that a shared object is mapped

  46. Private object • private object • As oppose to shared object • Changes made to an area mapped to a private object are not visible to other processes • Any writes that the process makes to the area are not reflected back to the object on disk. • private area • Similar to shared area

  47. Figure 10.31 (a) P725

  48. Figure 10.31 (b) P725

  49. Figure 10.32 (a) P726

  50. Figure 10.32 (b) P726

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