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Elements of Computer Design. Why is the computer the jewel in the crown of digital devices? Church-Turing Hypothesis Minimum requirements i) There must be a means to iterate through a group of instructions. ii) There must be a means of conditionally branching to another instruction.
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Elements of ComputerDesign Why is the computer the jewel in the crown of digital devices? Church-Turing Hypothesis Minimum requirements i) There must be a means to iterate through a group of instructions. ii) There must be a means of conditionally branching to another instruction. iii) The instructions must be complete relative to the task at hand.
Elements of ComputerDesign Computer Organization
Elements of ComputerDesign Memory Tristate buffer
Elements of ComputerDesign Memory 4 2-bit memories
Elements of ComputerDesign Memory 8 2-bit memories with 2 decoders
Elements of ComputerDesign Memory 8 4-bit memories with two 8 2-bit chips
Elements of ComputerDesign Memory 16 2-bit memories with two 8 2-bit chips
Elements of ComputerDesign CPU organization
Elements of ComputerDesign CPU Register Set (simplified)
Elements of ComputerDesign CPU Instruction Set (simplified)
Elements of ComputerDesign CPU Fetch Decode Execute Cycle F1: AR PC F2: DR M PC PC + 1 D: IR DR[6..4] AR DR[3..0] E1: AC M E2: M AC E3: R M E4: PC AR E5: AC AC + R E6: AC AC – R E7: AC AC OR R E8: AC AC AND R
Elements of ComputerDesign CPU control
Elements of ComputerDesign CPU ALU
Elements of ComputerDesign CPU Sample program LDA 13 ; load AC from address 13 LDR 14 ; load R from address 14 ADD ; add AC and R LDR 12 ; load R from address 12 SUB ; subract R from contents of AC LDR 11 ; load R from address 11 IOR ; OR R with contents of AC LDR 10 ; load R from address 10 AND ; AND R with contents of AC STA 14 ; store final result in address 14
Elements of ComputerDesign I/O organization
Elements of ComputerDesign I/O example
Elements of ComputerDesign Summary of topics Motivation Memory tristate buffers addressing addressing w/ mulitple decoders larger memories cascading memories CPU organization instruction set register set fetch-decode-execute control ALU I/0