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I NTERCONNECT M ODELING M.Arvind 2 nd M.E Microelectronics

I NTERCONNECT M ODELING M.Arvind 2 nd M.E Microelectronics. OVERVIEW. Introduction to On-Chip interconnects Modeling the parasitics Elmore Delay Model Repeater insertion Min delay condition Power Model Optimizing Power. Introduction to On-chip interconnects.

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I NTERCONNECT M ODELING M.Arvind 2 nd M.E Microelectronics

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  1. INTERCONNECT MODELINGM.Arvind2nd M.E Microelectronics

  2. OVERVIEW • Introduction to On-Chip interconnects • Modeling the parasitics • Elmore Delay Model • Repeater insertion • Min delay condition • Power Model • Optimizing Power

  3. Introduction to On-chip interconnects • Wires linking the transistors together • Three types of interconnects : • Local • Semi-global and • Global interconnect

  4. Introduction to On-chip interconnects • Can be modeled as R, RC, LC, RLC or RLGC network.

  5. Modeling a piece of wire

  6. Capacitance Modeling • Capacitance • cw= 2 * (cg + cf * cc ) • cf is the coupling factor

  7. Capacitance Modeling (cont) • cg has 2 components: cg1, cg2

  8. Simplified Capacitance Model • For a circuit designer • ILDT, h and ε are fixed. Therefore,

  9. Fringing Effects

  10. Modeling Wire Resistance • Resistance

  11. Pros and Cons of Cu • Pros • Better electro-migration resistance • Cons • Cu atoms diffuses into SiO2 • Cladding layers of TiN, Si3N4 used to prevent this • Increases the resistance

  12. Elmore Delay Model • Delay of a RC network is given by

  13. Delay of a long wire • Delay grows quadratic • Hence need repeaters

  14. Repeater Insertion • Repeaters are placed to reduce delay

  15. Repeater Insertion (cont) • Delay grows linear

  16. Modeling the repeater • Repeater is a large inverter (5-25μm) placed in-between interconnect lines. • Cgate,Cp α size of the repeater • RT = VDD/2*Iavg, where Iavg = ∫Iddt in the interval Td

  17. Modeling the repeater (cont)

  18. Delay equations • Delay of an interconnect segment is • Total delay is

  19. Optimal Repeater Size and Spacing • The minimum delay condition

  20. Total power dissipated in the interconnect network is given by Ptotal= Pdy + Psc + Pleak Pdy = Ctotal V²ddf Psc = Isc per μmVdd Wtotalftt Pleak = Ileak per μm WtotalVdd Where  is the switching factor, tt is the time taken for the input to transit from Vthn to Vdd – Vthp Power modeling

  21. Powermodeling (cont)

  22. Optimizing power • Min delay does not imply min power

  23. Can be reduced by decreasing Supply voltage Size of repeaters Number of repeaters Techniques to Reduce Power

  24. Optimal Power Delay Tradeoff

  25. References • William J.Dally John W.Poulton., ”Digital Systems Engineering” Cambridge University Press,1998 • Kaustav Banerjee et al., ”A power-optimal insertion methodology for global interconnects in nanometer designs” IEEE TRANSACTION ON ELECTRON DEVICES, VOL. 49, NO. 11, NOVEMBER 2002 • Kaustav Banerjee et al., ”A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation” IEEE TRANSACTION ON ELECTRON DEVICES. VOL. 51, NO.2, FEBRUARY 2004.

  26. Thank You

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