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CSCI-660 Introduction to VLSI Design

CSCI-660 Introduction to VLSI Design. Khurram Kazi. Verification Strategies: Motivation behind the verification efforts. Never under-estimate the verification effort of a design Keep in mind Non-recurring Engineering ASICs costs are very high

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CSCI-660 Introduction to VLSI Design

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  1. CSCI-660Introduction to VLSI Design Khurram Kazi

  2. Verification Strategies: Motivation behind the verification efforts • Never under-estimate the verification effort of a design • Keep in mind Non-recurring Engineering ASICs costs are very high • High upfront $ to get handful of sample chips from the foundry • The design is cast in “stone”, i.e. printed on Si • Any bugs or changes to the design cost in terms of time, $, market share, credibility with your customers, potential law-suits etc. Kazi Spring 2008 CSCI 660

  3. Pay extra attention to the verification efforts • In large complex ASICs, at times 70%+ of the project time is spent on ASIC verification. So pay close attention to it while designing. • This is a relatively new field (so to speak) where newer ways have to be used in order to verify the design for 1st time success. • Verification effort can be reduced through abstraction • However, this requires additional training. Languages like SystemC and System Verilog are gaining popularity in design verification of complex designs • Verification time can be reduced by using automation Kazi Spring 2008 CSCI 660

  4. When should the verification effort start • During the specification of the device, verification methodology should begin also. • Develop the verification architecture and build a comprehensive environment. • Think carefully how testbenches need to be developed. Just don’t throw code at it. Have systems perspective in mind, along with various stages of verification Kazi Spring 2008 CSCI 660

  5. Levels of verification System Board Multiple ASICs or FPGAs Most likely ASIC designers will have to make provisions for all these levels of verification Try to develop testbench such that it can be re-used at various levels or verification Single ASIC or FPGA Top level Block Sub-blocks Kazi Spring 2008 CSCI 660

  6. Example of a Multi ASIC verification environment Tx of ASIC 1 Rx of ASIC 1 Pattern Generator (1) Analyzer (1) Pattern Generator (2) Tx of ASIC 2 Rx of ASIC 2 ASIC 4 Analyzer (2) Pattern Generator (3) Tx of ASIC 3 Rx of ASIC 3 Analyzer (3) Kazi Spring 2008 CSCI 660

  7. Sample architecture of a generator and analyzer Tb_testcase1.vhd Global signals and control of tests; Global signals values are set at this level Global signals can be used to as expected values of out of ASIC Transmitter.vhd ASIC Analyzer.vhd Tb_dcom1 Tb_dcom2 Tb_frame_length …. Kazi Spring 2008 CSCI 660

  8. Tasks and Functions in Verilog • Same functionality is frequently required to be implemented in many places. The implies that commonly used portions of the design should be abstracted into routines and these routines should be invoked instead of repeating the code. • Verilog provides tasks and functions to break up large behavioral design into smaller pieces. • Tasks and functions in Verilog allow the designer to abstract the commonly used code that is used in many places Kazi Spring 2008 CSCI 660

  9. Functions in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros • Functions in Verilog have a declaration statements and a body. In the declaration, the size (dimension), type, and name of the output are specified, as well as the names and sizes (dimensions) of the inputs. e.g., the declaration statement: function exp input a, b; Declares a function with a name “exp”. The functions has two inputs, a and b, and one output, exp. Kazi Spring 2008 CSCI 660

  10. Functions in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros function [3:0] grt; /* The above function declares a function by the name grt; grt is also the output of the functions */ input signed [3:0] a, b; /* The above statement declares two inputs to the function; both are 4-bit signed numbers. */ begin if (a >= b) grt = a; else grt = b; end endfunction endmodule module greater_2 (x, y, z) input signed [3:0] x, y; output signed [3:0] z; reg signed [3:0] z; always @ (x,y) begin z = grt (x,y); // This is a function call end Kazi Spring 2008 CSCI 660

  11. Tasks in Verilog • Tasks are declared with keywords task and endtask. • The format of the task is divided into two parts • declaration • Name of the task is specified along with the inputs and outputs of the task • body • Describes the relationships between the input and outputs Kazi Spring 2008 CSCI 660

  12. Sample code of a task in Verilog module task_ex; integer a, b, c, d; initial begin a = 3; b = 4; d = 12; add (a, c, d); //Notice.. here the port mapping is positional $display (" final valus for c = %d", c); end task add; input [31:0] in1; output [31:0] out; //Notice this maps to "c" input [31:0] in2; out = in1 + in2 + d; //Notice here the value of "d" is defined in the module; it is a global variable endtask // add endmodule // task_ex Kazi Spring 2008 CSCI 660

  13. File Processing in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros • $fopen • The task $fopen is used to open files. The format for opening a file is channel = $fopen (“name of the file”); The channel is a variable of type integer; it indicates the channel number. Verilog uses this channel number to track and identify which files are open. Verilog automatically assigns an integer value to each channel. For example, to open a text file names testfile, we can write ch1 = $fopen(testfile.txt”); ch1 becomes the indicator (identifier) of the file testfile.txt Kazi Spring 2008 CSCI 660

  14. File Processing in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros • $fclose • The task $fclose is used to close a file indicated by the channel number. e.g., $fclose(ch1); closes the file “testfile.txt” • $fdisplay • The task $fdisplay is used to write variables, signals or quoted strings. The format of $fdisplay is as follows: $fdisplay (channel1, V1, V2, V3, …); where V1, V2, V3 … are variable, signals, or quoted strings. e.g., $fdisplay (ch1, “item description quantity”); After executing the task, the file testfile.txt will display item description quantity Kazi Spring 2008 CSCI 660

  15. File Processing in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros • $fmonitor • The task $fmonitor is used to monitor and record values of variables signals etc. $fmonitor (channel, v1, v2, v3, …); e.g. $fmonitor (ch1, “ %b”, quantity); The above task monitors quantity and records its value in binary in the file testfile.txt, indicated by ch1; %b indicates binary format. If quantity = 7 in decimal, after execution of the above task, the file testfile.txt looks like: item description quantity (from the previous slide) 111 %d Display in decimal %h Display in hex etc. Escape characters may also be used \n insert a blank line \t Insert tab etc. Kazi Spring 2008 CSCI 660

  16. $fgets( ) and $sscanf( ) $fgets( ) Gets string from a stream e.g. $fgets (str, file4) $sscanf( ) Read formatted data from string Reads data from str and stores them according to the parameter format into the locations give by the additional arguments. See example in the next slide Kazi Spring 2008 CSCI 660

  17. Text I/O in Verilog: Used for testbench purposes module txtio3 (out1, out2, out3, clk); output [15:0] out1; output [15:0] out2; output [15:0] out3; output clk; reg [15:0] out1, out2, out3; reg [4*8*4:1] str; reg clk; reg [15:0] a, b, c; integer file4, rc, line=0; initial begin file4 = $fopen("file4.txt", "r"); if (file4 == 0) $finish; clk = 0; forever #10 clk = !clk; end always @ (posedge clk) begin rc = $fgets (str, file4); rc = $sscanf (str, "%h %h %h\n", a, b, c); $display ( "\tLine %d read %h,\t%h, \t%h", line, a, b, c); out1 <= a; out2 <= b; out3 <= c; line = line +1; if (rc == 0) begin $fclose (file4); $finish; end end // always @ (posedge clk) endmodule // txtio3 File that is being read (“file4.txt”) 0001 0002 0003 0030 0040 0050 aa10 bb10 cc2b fff1 f210 ffe1 Kazi Spring 2008 CSCI 660

  18. Simulation Results Kazi Spring 2008 CSCI 660

  19. Packages in VHDL • Frequently used pieces of VHDL code are written in the form of Components, Functions, or Procedures • Such code can be placed in a Package and compiled into a destination Library • This allows code partitioning, code sharing and code reuse Kazi Spring 2008 CSCI 660

  20. Packages in VHDL • Package can contain • Components • Functions • Procedure • Type and constant definitions • Syntax of a package PACKAGE package_name IS (declarations) END package_name; [PACKAGE BODY package_name IS (functions and procedures descriptions) END package_name;] Kazi Spring 2008 CSCI 660

  21. Packages in VHDL: A Simple Package LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE my_package IS TYPE state is (st1, st2, st3, st4); TYPE color is (red, green, blue); CONSTANT F628 : STD_LOGIC_VECTOR (15 downto 0) := “1111_0110_0010_1000”; SIGNAL TB_DCOM1: STD_LOGIC_VECTOR (7 downto 0); END my_package; Kazi Spring 2008 CSCI 660

  22. Functions in VHDL • A FUNCTION is a section of sequential code • Operations like data type conversions, logical operations, arithmetic computations etc., can be created as functions Function Body FUNCTION function_name [<parameter list>] RETURN data_type is [declarations] BEGIN (sequential statements) END fucntions_name; Kazi Spring 2008 CSCI 660

  23. Functions in VHDL Function conv_integer (SIGNAL vector :STD_LOGIC_VECTOR) RETURN INTEGER IS; VARIABLE result : INTEGER RANGE 0 to 2**vector’LENGTH -1; BEGIN IF (vector’HIGH) = ‘1’) THEN result :=1; ELSE result := 0; END IF; FOR I IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP result := result * 2; IF (vector(i) = ‘1’) THEN result := result+1; END IF; END LOOP; RETURN result; END conv_integer; -----Function call----- ….. y <= conv_integer (a); …. --------------------------- Kazi Spring 2008 CSCI 660

  24. Procedures in VHDL • Procedure is similar to a Function, however, it can return more than one value • Procedure Body PROCEDURE precedure_name [<parameter lisr.] IS [declarations] BEGIN (sequential statements) END procedure_name; Kazi Spring 2008 CSCI 660

  25. Procedures in VHDL PROCEDURE sort ( SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255; SIGNAL min, max: OUT INTEGER RANGE 0 TO 255) IS BEGIN IF (in1 > in2) THEN max <= in1; min <= in2; ELSE max <= in2; min <= in1; END IF; END sort; Kazi Spring 2008 CSCI 660

  26. Locations of Procedures and Functions in VHDL • Functions and Procedures can be placed in • PACKAGE • Where the Package is compiled in a Library • Main Code Kazi Spring 2008 CSCI 660

  27. Locations of Procedures and Functions in VHDL -----Package: ---- LIBRARY ieee; USE ieee.std_logic_1164; Package my_package IS Function conv_integer (SIGNAL vector :STD_LOGIC_VECTOR) RETURN INTEGER IS; PROCEDURE sort ( SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255; SIGNAL min, max: OUT INTEGER RANGE 0 TO 255) IS END my_package; PACKAGE BODY my_package IS PROCEDURE sort ( SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255; SIGNAL min, max: OUT INTEGER RANGE 0 TO 255) IS BEGIN IF (in1 > in2) THEN max <= in1; min <= in2; ELSE max <= in2; min <= in1; END IF; END sort; Copy the Function code here if you want to add any functions to the package END my_package; Compile the package in the work.lib In the main code of the design or the testbench the package can be called as Library ieee; USE ieee.std_logic…. USE work.my_package.all ……. Kazi Spring 2008 CSCI 660

  28. Text I/O to/from Files library ieee; use ieee.std_logic_1164.all; use std.textio.all; ENTITY txtio is port(start : in STD_LOGIC; z, z1, z2, z3 : out integer); end txtio; architecture integer_proc of txtio is begin process -- declare the infile as a text file file infile : text; --declare variable fstatus (or any other variable name) -- as of type file_open_status variable fstatus : file_open_status; variable count : integer; --declare variable temp as the type line variable temp : line; begin wait for 1 ns; --open the file file_int.txt in read mode file_open (fstatus, infile, "file_int.txt", read_mode); --read the first line of the file and store the line in temp readline (infile, temp); --temp now has the data: 12 -3 5 -- Read the first integer (12) from the line temp and store it -- in the integer variable count. read (temp, count); -- count has the value of 12. Multiply by 2 and store in z z <= 2 * count; -- Read the second integer from the line temp and --store it in count read (temp, count); -- now count has a value of -3 --Multiply by 5 and store in z1 z1 <= 5 * count; -- Read the third integer from the line temp and --store it in count read (temp, count); -- now count has a value of 5 --Multiply by 3 and store in z2 z2 <= 3 * count; --Read the second line and store it in temp readline (infile, temp); --temp has only the second line --Read the first integer of the second line and store it in count read (temp, count); --Multiply by 4 and store in Z3 z3 <= 4 * count; --close the infile file_close (infile); end process; end integer_proc; Kazi Spring 2008 CSCI 660

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