Using Hierarchy in Design Automation: The Fault Collapsing Problem

1. Raja K. K. R. Sandireddy Intel Corporation Hillsboro, OR 97124, USA raja.sandireddy@intel.com Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA vagrawal@eng.auburn.edu Using Hierarchy in Design Automation: The Fault Collapsing Problem 11thVLSI Design and Test Symposium Kolkata, August 8-11, 2007

2. Outline • Introduction • Main idea • Background on fault collapsing • Hierarchical fault collapsing • Method • Advantages: • Smaller collapse ratio • Reduced CPU time • Results • Conclusion VDAT: Sandireddy & Agrawal

3. The General Idea of Hierarchy Lowest-level block (gates and interconnects), analyzed in detail, saved in library. Circuit (top level In hierarchy) Subnetwork analyzed once, placed in library. interconnects Analysis at nth level: 1. Copy preprocessed internal detail of n-1 level from library. 2. Process nth level interconnects. VDAT: Sandireddy & Agrawal

4. Background on Fault Collapsing Test Vector Generation Flow DUT Generate fault list Collapse fault list Generate test vectors Fault model Required fault coverage VDAT: Sandireddy & Agrawal

5. Structural Fault Collapsing • Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set. • Equivalence collapsed set = {a0, b0, c0, c1} • Collapse ratio = 4/6 = 0.67 • Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults. • Dominance collapsed set = {a0, b0, c1} • Collapse ratio = 3/6 = 0.5 Total faults = 6 VDAT: Sandireddy & Agrawal

6. Functional Collapsing: XOR Cell Functional dominance examples: d0 → j0, k1→ g0 c0 c1 All faults = 24 Str. Equ. Faults = 16 Str. Dom. Faults = 13 Func. Dom. Faults = 4 c d0 d1 h j a g m d e b k i f VDAT: Sandireddy & Agrawal

7. Hierarchical Fault Collapsing • Create a library • For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done. • For larger circuits, use structural collapsing. • For hierarchical circuits, at any level of hierarchy, say nth level: • Read-in preprocessed (library) collapse data of (n-1) level sub-circuits. • Structurally collapse the interconnects and gate faults of nth level. • R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014–1019. • R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176. VDAT: Sandireddy & Agrawal

8. A Fault Collapsing Library *Sun Ultrasparc 5_10 (360MHz, 128MB) VDAT: Sandireddy & Agrawal

9. Collapse Ratios for Ripple-Carry Adders Collapse ratio Total faults 234 1,858 14,850 118,786 475,138 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed. Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program (Auburn Univ.) VDAT: Sandireddy & Agrawal

10. CPU Time (sec) Improvement by Hierarchy for Ripple-Carry Adder VDAT: Sandireddy & Agrawal

11. G is proportional to area Rent’s rule • Rent’s Rule: Number of inputs and outputs terminals (T) for a typical block containing G logic gates is given by: T = K × Gα α~ 0.5 to 0.65 • CPU time for collapsing a large hierarchical circuit is dominated by the time taken to build the structure of the circuit which is proportional to the T 2 (ref: our previous work). VDAT: Sandireddy & Agrawal

12. Hierarchical Ripple-Carry Adder Here α ~ 1.0, hence the total collapse time is quadratic in circuit size as observed in our experiment. VDAT: Sandireddy & Agrawal

13. n/2×n/2 Additional Circuitry Hierarchical Array Multiplier n × n multiplier n/2×n/2 n/2×n/2 n/2×n/2 Inputs Outputs prop. to √G prop. to √G Here α ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size. VDAT: Sandireddy & Agrawal

14. Collapse Ratios for Array Multipliers Collapse ratio Total faults 84 726 3762 16,842 71,034 291,546 1,181,082 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed. Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program (Auburn Univ.) VDAT: Sandireddy & Agrawal

15. CPU Time Improvement by Hierarchy for Array Multipliers VDAT: Sandireddy & Agrawal

16. Conclusion • Benefits of hierarchical fault collapsing: • Better (lower) collapse ratios due to functional collapsing of library cells. • Order of magnitude reduction in collapse time. • Possible benefits of smaller fault sets: • Fewer test vectors • Efficient fault simulation • Easier fault diagnosis • Further investigations: • Structural problems (testability measures, static timing analysis, physical design, etc.) may be solved using hierarchy. • Functional problems (ATPG, simulation, etc.) may require new hierarchical algorithms. 128-bit multiplier VDAT: Sandireddy & Agrawal