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Use of Hierarchy in Fault Collapsing

This article discusses the use of hierarchy in fault collapsing, highlighting its advantages and providing an analysis of CPU time. The results show improved collapse ratios and reduced CPU time compared to non-hierarchical methods.

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Use of Hierarchy in Fault Collapsing

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  1. Use of Hierarchy in Fault Collapsing Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA Raja K. K. R. Sandireddy Intel Corporation Hillsboro, OR 97124, USA Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  2. Outline • Introduction • Main idea • Background on fault collapsing • Hierarchical fault collapsing • Method • Advantages: • Smaller collapse ratio • Reduced CPU time • Results • Conclusions Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  3. The General Idea of Hierarchy Lowest-level block (gates and interconnects), analyzed in detail, saved in library. Circuit (top level In hierarchy) Subnetwork analyzed once, placed in library. interconnects Analysis at nth level: 1. Copy preprocessed internal detail of n-1 level from library. 2. Process nth level interconnects. Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  4. Background on Fault Collapsing Test Vector Generation Flow DUT Generate fault list Collapse fault list Generate test vectors Fault model Required fault coverage Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  5. Structural Fault Collapsing • Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set. • Equivalence collapsed set = {a0, b0, c0, c1} • Collapse ratio = 4/6 = 0.67 • Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults. • Dominance collapsed set = {a0, b0, c1} • Collapse ratio = 3/6 = 0.5 Total faults = 6 Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  6. Functional Collapsing: XOR Cell Functional dominance examples: d0 → j0, k1→ g0 c0 c1 All faults = 24 Str. Equ. Faults = 16 Str. Dom. Faults = 13 Func. Dom. Faults = 4 c d0 d1 h j a g m d e b k i f Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  7. Hierarchical Fault Collapsing • Create a library • For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done. • For larger circuits, use structural collapsing. • For hierarchical circuits, at any level of hierarchy, say nth level: • Read-in preprocessed (library) collapse data of (n-1) level sub-circuits. • Structurally collapse the interconnects and gate faults of nth level. • References: • R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014–1019. • R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176. Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  8. Results: Collapse Ratio Advantage Collapse ratio Total faults 60 3,714 59,394 1,116 2,646 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder) are functionally collapsed. Programs used: 1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  9. Fault Collapsing Time for Flattened Circuits CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory. Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  10. Analysis of CPU Time (s) for Flattened Circuits Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  11. Analysis of CPU Time (s) for Hierarchical Circuits Structure Processing Equiv.+Dom.Collapsing Library Total 64-bit 0.01 0.01 0.07 0.10 128-bit 0.03 0.02 0.13 0.19 256-bit 0.05 0.02 0.19 0.39 512-bit 0.17 0.04 0.36 0.81 1024-bit 0.55 0.08 0.73 1.82 2048-bit 2.10 0.20 1.52 4.72 4096-bit 9.25 0.37 3.1 14.3 8192-bit 40.1 0.79 6.0 50.2 Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  12. Comparison of CPU Times for Hierarchical and Flattened Circuits Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  13. CPU Time (s) Improvement by Hierarchy Flattened circuit Hierarchical circuit Hitec Our Program Two-level Multi-level 64-bit 0.57 0.24 0.16 0.10 128-bit 1.47 0.75 0.32 0.24 256-bit 5.09 2.49 0.69 0.49 512-bit 19.5 9.38 1.52 1.05 1024-bit 77.7 39.9 3.60 2.31 2048-bit 326 166.4 10.3 4.80 4096-bit 1258 674.1 35.1 16.6 8192-bit -- 2676 127.2 55.0 Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  14. CPU time (s) for Hierarchical Collapsing Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  15. Rent’s rule • Rent’s Rule: Number of inputs and outputs terminals (T) for a typical block containing G logic gates is given by: T = K × G ~ 0.5 to 0.65 • For ripple carry adders, ~ 1. CPU time for collapsing is proportional to G2. G is proportional to area a Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  16. n/2×n/2 Additional Circuitry Hierarchical Multipliers n × n multiplier n/2×n/2 n/2×n/2 n/2×n/2 ~ √G outputs ~ √G inputs Here ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size. Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  17. Conclusions • For larger circuits described hierarchically, use hierarchical fault collapsing. • Hierarchical fault collapsing: • Better (lower) collapse ratios due to functional collapsed library • Order of magnitude reduction in collapse time. • Smaller fault sets: • Fewer test vectors • Reduced fault simulation effort • Easier fault diagnosis. 8192-bit Adder Sandireddy & Agrawal: Hierarchy in Fault Collapsing

  18. THANK YOU Sandireddy & Agrawal: Hierarchy in Fault Collapsing

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