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Hierarchical Fault Collapsing for Logic Circuits

Master’s Defense Raja K. K. R. Sandireddy Dept. of ECE, Auburn University. Hierarchical Fault Collapsing for Logic Circuits. Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud Dept. of ECE, Auburn University. Outline. Introduction Background

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Hierarchical Fault Collapsing for Logic Circuits

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  1. Master’s Defense Raja K. K. R. Sandireddy Dept. of ECE, Auburn University Hierarchical Fault Collapsing for Logic Circuits Thesis Advisor:Vishwani D. Agrawal Committee Members:Victor P. Nelson, Charles E. Stroud Dept. of ECE, Auburn University

  2. Outline • Introduction • Background • Fault Equivalence and Fault Dominance • Functional collapsing • Hierarchical fault collapsing • Fault Equivalence and Dominance definitions • Algorithm to find dominance relations • Results of functional collapsing • Hierarchical fault collapsing • Results of hierarchical fault collapsing • Conclusions and Future work Raja Sandireddy: MS Defense

  3. Introduction Test Vector Generation Flow DUT Generate fault list Collapse fault list Generate test vectors Fault model Required fault coverage Raja Sandireddy: MS Defense

  4. Stuck-at Fault • Single stuck-at fault model is the most popular model. a0 a1 a c0 c1 c b0 b1 b • Subscript fault notation: a0 means stuck-at-0 on line a. Raja Sandireddy: MS Defense

  5. Equivalence Structural R-equivalence1: Two faults f1 and f2 are said to be R-equivalent if they produce the same reduced circuit graph [netlist] when faulty values are implied and constant edges [signals] are removed. Functional F-equivalence1: Two faults f1 and f2 are said to be F-equivalent if they modify the Boolean function of the circuit in the same way, i.e., they yield the same output functions. 1 E. J. McCluskey and F. W. Clegg, “Fault Equivalence in Combinational Logic Networks,” IEEE Trans. Computers, vol. C-20, no. 11, Nov. 1971, pp. 1286-1293. Raja Sandireddy: MS Defense

  6. Structural Equivalence a a 0 1 a1 ≡ b1≡ c1 : Equivalence c c 0 1 b b 0 1 Equivalent faults are indistinguishable at all primary outputs of the circuit. Raja Sandireddy: MS Defense

  7. Structural Dominance A fault fi is said to dominate fault fj if the faults are equivalent with respect to test set of fault fj. Dominance relations a0 c0 b0 c0 a1 c1 a1  c1 b1 c1 b1 c1 a1 b1 a1 b1 a a 0 1 Equivalence Relations c c } } } } 0 1 a1 ≡ c1 b1≡ c1 a1≡ b1 a1 ≡ b1≡ c1 b b 0 1 Raja Sandireddy: MS Defense

  8. Fault Collapsing • Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set. • Dominance Collapsing: From the equivalence collapsed set, all the dominating faults are left out retaining their respective dominated faults. For the OR gate, Equivalence collapsed set = {a0, b0, c0, c1} Dominance collapsed set = {a0, b0, c1} Raja Sandireddy: MS Defense

  9. Collapse Ratio Example: Full adder circuit. Total faults: 60 Structural equivalence collapsed set2, 3 = 38 (0.63) Structural dominance collapsed set3 = 30 (0.5) 2 Using Hitec: T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218. 3 Using Fastest: T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993. Raja Sandireddy: MS Defense

  10. Dominance Graph A 2-input OR gate and its dominance graph Dominance Matrix a c b Used for fault collapsing. Raja Sandireddy: MS Defense

  11. Two Algorithms: Equivalence and Dominance4 Algorithm Equivalence 1 1 1 1 1 1 1 1 Algorithm Dominance 4 A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets,” Proc. International Test Conf., Oct. 2002, pp. 391-397. Raja Sandireddy: MS Defense

  12. F1 Z F2 Functional Equivalence F1 Z If faults in blocks F1 and F2 are equivalent, then Z≡ 0. F0 F2 For the full-adder, functional equivalence collapsed set = 26 (0.43). {Structural equiv. = 38, Structural dom. = 30} Raja Sandireddy: MS Defense

  13. Functional Dominance5 F1 1 Z F0 0 1 F2 If the fault introduced in block F1 dominates the fault in block F2, then Z is always 0. For the full adder, functional dominance collapsed set = 12 (0.20) {Structural equiv. = 38, Structural dom. = 30, Functional equiv.= 23} 5 V. D. Agrawal, A. V. S. S. Prasad, and M. V. Atre, “Fault Collapsing via Functional Dominance,” Proc. International Test Conf., 2003, pp. 274-280. Raja Sandireddy: MS Defense

  14. Hierarchical Circuits Increasing complexity of designs is efficiently handled by hierarchical design process. Hierarchical fault collapsing: • Create a library • For smaller sub-circuits, exhaustive collapsing is done using the methods discussed earlier. • For larger sub-circuits, use structural collapsing. • At the top level, do structural collapsing using the library information to collapse the faults at lower levels. Raja Sandireddy: MS Defense

  15. Hierarchical Fault Collapsing Advantages: • Fault set computed once is reused for all instances of the sub-circuit. • Exhaustive collapsing of faults in smaller circuits to achieve smaller collapsed sets. • Faster collapsing. Theorem6: If two faults are functionally equivalent in a sub-circuit Ci that is embedded in a circuit Cj then they are also functionally equivalent in Cj . Note: Functional equivalence here means diagnostic equivalence as defined next. 6 R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176. Raja Sandireddy: MS Defense

  16. Equivalence Definitions • Fault Equivalence: Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions. For multiple output circuits, this is extended for two possible interpretations. • Diagnostic Equivalence - Two faults of a Boolean circuit are called diagnostically equivalent if and only if the pair of the output functions is identical at each output of the circuit. • Detection Equivalence - Two faults are called detection equivalent if and only if all tests that detect one fault also detect the other fault, not necessarily at the same output. For single output circuits, diagnostic and detection equivalence mean the same. Diagnostic equivalence implies detection equivalence. Raja Sandireddy: MS Defense

  17. A s-a-0 Y B Z c s-a-0 Examples to Demonstrate Detection Equivalence s-a-1 Q The faults P1, Q1 and R1 are detection equivalent faults, but not diagnostic equivalent. s-a-1 P s-a-1 R The faults c0 and Y0 are detection equivalent faults, but not diagnostic equivalent. For the full adder, diagnostic equivalence collapsed set = 26 (0.43), detection equivalence collapsed set = 23 (0.38) {Structural equiv. = 38, Structural dom. = 30,Functional equiv.= 26, Functional dom.= 12} Raja Sandireddy: MS Defense

  18. Dominance Definitions • Fault Dominance7- A fault fi is said to dominate fault fj if (a) the set of all vectors that detects fault fj is a subset of all vectors that detects fault fi and (b) each vector that detects fj implies identical values at the corresponding outputs of faulty versions of the circuit. Conventionally dominance is defined as: • A fault fi is said to dominate fault fj if the faults are equivalent with respect to test set of fault fj. • If all tests of fault fj detect another fault fi, then fi is said to dominate fj. 7 J. F. Poage, “Derivation of Optimum Tests to Detect Faults in Combinational Circuits", Proc. Symposium on Mathematical Theory of Automata, 1962, pp. 483-528. Raja Sandireddy: MS Defense

  19. Dominance Definitions Contd. For multiple output circuits, the two possible interpretations of dominance: • Diagnostic dominance - If all tests of a fault f1 detect another fault f2 on the exact same outputs where f1 was detected, then f2 is said to diagnostically dominate f1. • Detection dominance - If all tests of a fault f1 detect another fault f2, irrespective of the output where f1 was detected, then f2 is said to detection dominate f1 . Diagnostic dominance implies detection dominance. For the full adder, diagnostic dominance collapsed set = 12 (0.2) detection dominance collapsed set = 6 (0.1) {Structural equiv. = 38,Structural dom. = 30,Diagnostic equiv.= 26, Detection equiv.= 23} Raja Sandireddy: MS Defense

  20. D or D D or D Functional Dominance Faults in this circuit are checked for redundancy F0 0 F0 1 0 F1 Fault introduced in this circuit Raja Sandireddy: MS Defense

  21. Algorithm to Find All Dominance Relations • Select a fault from the given circuit and build the circuit as shown in previous slide with the fault introduced in the bottom block whose function is F1. • Check for redundant faults in the top block, F0. • For each redundant fault found in step 2, a 1 is placed in the dominance matrix at the intersection of the row corresponding to the redundant fault and the column corresponding to the fault in the bottom block. Thus, we obtain all values of a column of the dominance matrix in a single iteration. • Go to step 1 until there is no fault left. • Now we will have the dominance matrix with all the functional dominance relations included. Raja Sandireddy: MS Defense

  22. Algorithm Contd. • Transitive closure of the dominance matrix is computed, which is then reduced using algorithm equivalence4. This reduced matrix still consists of dominance relations within an equivalence collapsed set of faults. • If dominance collapsing is required, then the reduced matrix of the previous step is further reduced according to algorithm dominance4. For simplicity, the redundant faults of the given circuit (stand-alone F0) are not considered in step 1. 4 A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets,” Proc. International Test Conf., Oct. 2002, pp. 391-397. Raja Sandireddy: MS Defense

  23. For Multiple Output Circuits For a circuit with 2 outputs, the schemes used to find the dominance relations: F0 F0 F0 F0 F1 F1 Diagnostic collapsing Detection collapsing Raja Sandireddy: MS Defense

  24. Results: Functional Collapsing 2 Using Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 3 Using Fastest (obtained from Univ. of Wisconsin at Madison) 5 Agrawal, et al. ITC’03 Raja Sandireddy: MS Defense

  25. Results: Test Vectors Test vectors obtained using Gentest ATPG8. 8 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989. Raja Sandireddy: MS Defense

  26. Hierarchical Fault Collapsing Line Oriented Structural Fault Collapsing9: 9 M. Nadjarbashi, Z. Navabi, and M. R. Movahedin, “Line Oriented Structural Equivalence Fault Collapsing,“ IEEE Workshop on Model and Test, 2000. Raja Sandireddy: MS Defense

  27. 0 Hierarchical Fault Collapsing G 1 1 0 A M 0 1 0 1 B G 4 1 0 1 0 G 2 G 3 1 0 C • Algorithm to find the dominance matrix and its transitive closure: • Consider a fault (f1) stuck-at-b at the input of a Boolean gate. • If the gate is of inverting type (NOT, NOR, NAND), then invert b. • If the equivalent set has s-a-b on this gate output, say f2,then return this fault – place a 1 at the intersection of the row corresponding to f1 and column corresponding to f2 – use Update10 for transitive closure. End. • Move one gate forward towards the primary output and go to step 2. 10 K. K. Dave, V. D. Agrawal, and M. L. Bushnell, “Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies,” Proc. 18th International Conf. VLSI Design, Jan. 2005, pp. 723-729. Raja Sandireddy: MS Defense

  28. G1 A M Circuit M B g1 a G4 G2 G3 b g3 C g2 Collapsed Information File as Saved in Library $RELATIONs: 1: 4 5 12 0 2: 6 13 0 3: 9 13 0 4: 1 5 12 0 5: 1 4 12 0 6: 2 13 0 9: 13 0 12: 1 4 5 0 13: 0 $REDUNDANT: g1(b,0) 14 $INPUTs: a 1 2 b* 3 4 $OUTPUTs: g3 12 13 $TOTAL: 14 $FAULTs: g1(0) 5 g1(1) 6 g2(1) 9 Collapsed fault set sizes Raja Sandireddy: MS Defense

  29. Results: Collapse Ratios Total Faults: Full adder: 60, 64-bit Adder: 3714, 1024-bit Adder: 59394, c432:1116, c499:2646 Detection collapsing can be used only for those sub-circuits whose outputs are POs at the top-level. Raja Sandireddy: MS Defense

  30. Flat Structure Processing Equivalence Collapsing Dominance Collapsing Total 64-bit 0.13 0.02 0.03 0.24 128-bit 0.54 0.05 0.05 0.75 256-bit 2.05 0.09 0.09 2.49 512-bit 8.60 0.17 0.20 9.38 1024-bit 38.3 0.36 0.41 39.9 2048-bit 163.1 0.74 0.84 166.4 4096-bit 667.4 1.49 1.63 674.1 8192-bit 2662 3.43 3.73 2676 CPU Time (s) for Different Sections of Our Program for Flattened Circuits CPU time clocked on a 360MHz Sun UltraSparc 5_10 machine with 128MB memory. Raja Sandireddy: MS Defense

  31. CPU Time (s) for Different Sections of Our Program for Flattened Circuits Raja Sandireddy: MS Defense

  32. CPU Time (s) of Different Commands of Hitec for Fault Collapsing Structure Processing (level) Equivalence Collapsing (equiv) Total 64-bit 0.32 0.16 0.57 128-bit 1.03 0.34 1.47 256-bit 4.0 0.88 5.09 512-bit 16.0 3.15 19.5 1024-bit 64.9 12.2 77.7 2048-bit 275.1 50.4 326 4096-bit 1045 210 1258 Raja Sandireddy: MS Defense

  33. Comparison of CPU Times (s) Taken by Hitec and Our Program Raja Sandireddy: MS Defense

  34. CPU Time (s) of Different Sections of Our Program for Hierarchical Circuits Structure Processing Equiv.+Dom.Collapsing Library Total 64-bit 0.01 0.01 0.07 0.10 128-bit 0.03 0.02 0.13 0.19 256-bit 0.05 0.02 0.19 0.39 512-bit 0.17 0.04 0.36 0.81 1024-bit 0.55 0.08 0.73 1.82 2048-bit 2.10 0.20 1.52 4.72 4096-bit 9.25 0.37 3.1 14.3 8192-bit 40.1 0.79 6.0 50.2 Raja Sandireddy: MS Defense

  35. CPU Time (s) of Our Program for Hierarchical and Flattened Circuits Raja Sandireddy: MS Defense

  36. CPU Time (s) Improvement by Hierarchy Flattened circuit Hierarchical circuit Hitec Our Program Two-level Multi-level 64-bit 0.57 0.24 0.16 0.10 128-bit 1.47 0.75 0.32 0.24 256-bit 5.09 2.49 0.69 0.49 512-bit 19.5 9.38 1.52 1.05 1024-bit 77.7 39.9 3.60 2.31 2048-bit 326 166.4 10.3 4.80 4096-bit 1258 674.1 35.1 16.6 8192-bit -- 2676 127.2 55.0 Raja Sandireddy: MS Defense

  37. CPU Time (s) for Hierarchical Collapsing Raja Sandireddy: MS Defense

  38. Conclusions • Diagnostic and detection collapsing should be used only with smaller circuits. • Collapse ratios using detection dominance collapsing is about 10-20%. • For larger circuits described hierarchically, use hierarchical fault collapsing. • Hierarchical fault collapsing: • Better (lower) collapse ratios due to functional collapsed library • Order of magnitude reduction in collapse time. • Smaller fault sets: • Fewer test vectors • Reduced fault simulation effort • Easier fault diagnosis. • Use caution when using dominance collapsing!! 8192-bit Adder Raja Sandireddy: MS Defense

  39. Future Work • Generate fault collapsing library of standard cells (Mentor Graphics, etc.) • Incorporate VHDL or Verilog input for hierarchical netlist. • Efficient redundancy detection program. • Customized ATPG to obtain minimal test vector set. • Extend the work for sequential circuits. • Extend the work for other fault models. Raja Sandireddy: MS Defense

  40. THANK YOU Raja Sandireddy: MS Defense

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