1 / 19

Design and Implementation of Turbo Decoders for Software Defined Radio

Design and Implementation of Turbo Decoders for Software Defined Radio. Yuan Lin 1 , Scott Mahlke 1 , Trevor Mudge 1 , Chaitali Chakrabarti 2 , Alastair Reid 3 , Krisztian Flautner 3 1 Advanced Computer Architecture Lab, University of Michigan

keely
Download Presentation

Design and Implementation of Turbo Decoders for Software Defined Radio

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design and Implementation of Turbo Decoders for Software Defined Radio Yuan Lin1, Scott Mahlke1, Trevor Mudge1, Chaitali Chakrabarti2, Alastair Reid3, Krisztian Flautner3 1Advanced Computer Architecture Lab, University of Michigan 2Department of Electrical Engineering, Arizona State University 3ARM, Ltd. 1

  2. Advantages of Software Defined Radio • Multi-mode operations • Lower costs • Faster time to market • Prototyping and bug fixes • Chip volumes • Longevity of platforms • Protocol complexity favors software dominated solutions • Enables future wireless communication innovations • Cognitive radio 2

  3. SDR Design Objectives for W-CDMA • Programmable processor • Same hardware should support Turbo decoder as well as other DSP algorithms • Throughput requirements • 2Mbps • Power constraints • 100mW ~ 500mW 3

  4. SODA: DSP Processor for SDR 4

  5. SODA PE SIMD Pipeline 5

  6. SODA PE SIMD Shuffle Network 6

  7. SODA PE Scalar Pipeline 7

  8. Turbo Decoder on SODA • Most computationally intensive algorithm in W-CDMA • Hardest algorithm to parallelize • Implementation outline • MaxLogMAP trellis computation with SIMD operations • Parallelizing trellis computations through sliding window • Interleaver implementation 8

  9. Trellis Computation on SODA • Two types of trellis diagram configurations • Blue edges: (0-branch),Red edges: (1-branch) • Mapping trellis of size S onto SODA of SIMD size T 9

  10. Misaligned SIMD operation Forward Trellis on SODA (S = T) 10

  11. Handling SIMD Misalignment 11

  12. Sliding Window on SODA • Problem: • W-CDMA uses K=4, 8 wide trellis • SODA has 32-wide SIMD • Solution: • parallelize trellis computation by implementing sliding window • fully utilize SIMD width • achieving higher-throughput in the process 12

  13. Sliding Window Parallelization 13

  14. Sliding Window on SODA (S < T) 14

  15. Turbo Decoder System Operations 15

  16. SODA DMA Modifications • Traditional DMA controller • Designed for block data transfer • 1 source and 1 destination address per block • Modified DMA controller • Adding data interleaving functionality to DMA • Needs to handle scalar data transfers • 1 source and 1 destination address per scalar 16

  17. Average number of cycles for one trellis block dummy calculation size of one trellis block data memory access 1 bit of Alpha, Beta and LLC computation 1 bit of Alpha, Beta and LLC computation SODA operation frequency Overall Turbo decoder throughput Number of sliding windows processed in parallel Extrinsic scaling Number of Turbo iterations Cycles for 1bit trellis computaion = Tblock/L Achieved Performance on SODA • SODA operates at 400MHz • Can achieve 2.08Mbps with I = 5 17

  18. Conclusion & Future Work • Implementation summary • SODA consumes <100mW in 90nm • Meets W-CDMA throughput requirements • Hardware features • wide SIMD execution • SIMD permutation network • smart DMA • Beyond 3G • Support for higher throughput 3G+ protocols • Multi-processor SODA for Turbo decoder • LDPC decoding 18

  19. Questions? • www.eecs.umich.edu/~sdrg 19

More Related