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Abderrezak Mekkaoui amekkaoui@lbl

Abderrezak Mekkaoui amekkaoui@lbl.gov. General Outline. NOTE: throughout this presentation, HEP denotes High Energy Physics and similar fields. Introduction A glance at the current ITRS roadmap for analog Some 65nm device test results Some examples of current projects FEI4 (ATLAS)

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Abderrezak Mekkaoui amekkaoui@lbl

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  1. AbderrezakMekkaoui amekkaoui@lbl.gov

  2. General Outline NOTE: throughout this presentation, HEP denotes High Energy Physics and similar fields • Introduction • A glance at the current ITRS roadmap for analog • Some 65nm device test results • Some examples of current projects • FEI4 (ATLAS) • ATPIX65 (LBNL) • APSEL(INFN) • MAPS (LBNL) • HIPPO (LBNL) • Vertical integration: 3D • Conclusions • Backup slides and extras

  3. Introduction Performance and functionality of integrated circuits continued to increase for the past few decades. Technology scaling (down) has fueled what is known as Moore’s law (or is it vice versa?): the number of components per chip roughly doubles every 24 months. Transistor dimensions (width, length and gate thickness) are continuously decreased and so are the metal pitch while the number of metal levels has been increased. Process optimization for some niche market (like RF) has also led to multi-threshold and multi-supply transistors along with high quality passives. While scaling down is still going on, industry experts are already introducing the concept of “more than Moore” to prevent the increase of performance of ICs from slowing down (physical scaling down will ultimately be unpractical). Without the advances in IC technology, some important HEP projects (at some crucial time) would have been not feasible or would have required specialized low yield low performance high cost processes. The future will be no different. Complex and challenging instrumentation projects (Upgrades, SLHS, new Detector concepts) will require the adoption of the ever more empowering (and more complex) IC technologies. This is exemplified by recent design activities using the 65nm CMOS node, which is the state of the art for this community. This talk will briefly describe some of the prototyping work in 65nm CMOS (mainly).

  4. Industry and HEP IC “nodes” 250nm, 70Mrad special layout 130nm, 250Mrad 65nm, >200Mrad Baschirotto, University of Milano-Bicocca “LV Analog Design in scaled CMOS technology” (image without the HEP figures) HEP projects, even though lagging mainstream technology, are benefitting from Technology scaling. There should be a “topical” Moore’s law. ICs are only one part of an instrumentation system! Is detector technology not keeping pace?

  5. ITRS performance RF/Analog roadmap Notice difference between Performance versus precision (next slide) ITRS key: Yellow=solution known but not optimized. Red= solution not known. http://www.itrs.net/

  6. ITRS Precision Analog/RF roadmap • Tox decreasing: better ionizing radiation resistance. Gate rupture? Other problems? • Gm/gds decreasing: Lower gain • 1/f noise decreasing. • Matching improving (barely and only for analog devices) • Speed increasing • Supply voltage decreasing: reduced Dynamic range. • Other: gate leakage, off current, variability of non analog transistors …

  7. The main design challenges (my experience) It is only a problem of degree. Analog design has always been about designing working circuits using imperfect devices. Good circuits were designed in NMOS only single metal Single poly processes! Read IEEE JSSC!

  8. ITRS bipolar Roadmap For specialized projects. Main challenge: breakdown voltage getting lower.

  9. Advanced IC processes are available thru brokers IBM CMOS (mosis) VDD TSMC CMOS (mosis)

  10. Advanced IC processes available thru brokers IBM BiCMOSSiGe (mosis) Other less advanced and specialized processes are available thru mosis, cmp, europractice And others! http://www.mosis.com http://cmp.imag.fr/ http://www.europractice-ic.com/ St Micro CMOS (cmp)

  11. Area reduction Highest for mostly digital systems For analog design, most of the challenges can be addressed by proper device selection and design. But at the expense of increased area: Reduce analog functionality to the minimum to benefit from the ever increasing integration density in advanced process. Analog “deficiencies” can be mitigated by special digital techniques. Die area reduction based on analog/digital mix (A. Baschirotto )

  12. Harnessing digital processing power (a physicist perspective) • Complex pattern recognition on chip • Cluster formation, including NN-style. • Rejection of background clusters- eg. from beam halo particles • Generic user-programmable DSP • Pulse shape analysis. • Digital corrections for anything and everything (eg. Time-walk). • Self-repairing or self-testing designs. Either 100% yield or chips that automatically report their quality upon power-up (second probably easier) • Self calibrating, self timing-in, etc. • No need to save and download threshold tunes, for example, because threshold is automatically tuned on-chip in real time. • Automating monitoring, interlocking, etc. • Configurable geometry. Not all pixels have to be used. User selects desired densitylower density = lower power and greater bump bonding pitch • Prompt hit processing (complex and fast processing of hits from pixel columns) M. Garcia-Sciveres, Atlas Upgrade Week 11/16/11

  13. Illustration of the Power of integration FEI4: 0.13m ATLAS Pixel ROC ~ 20mm X 20mm Size would probably remain the same if implemented in 65 nm >One 32bit ARM11 processor core Per 4 columns (65LP)! Fits in the dead area!

  14. 65nm: Some transistor test result • No noise degradation at lower nodes • No thermal noise increase with radiation • No or little 1/f noise increase with radiation Same gate capacitance M. Manghisoni et al. TWEPP 2011

  15. 65nm: Some radiation tolerance results Threshold voltage Leakage current S. Bonacini et al. TWEPP 2011 65 nm devices seem to outperform their 130nm counterparts in their tolerance to ionizing radiation !

  16. Example 1: FEI4A (ATLAS PIXELS FOR IBL) FEI4A 0.13u process Performs also most of a module Controller chip duties FEI3 0.25u process • Copes with higher hit rate: regional architecture and smaller pixel size • Improved cost effectiveness: Large chip with large active area • Lower power: Improved design and architecture • Increased radiation tolerance (~250Mrad)

  17. FEI4 (cont’d) • Column drain architecture (a la FEI3) saturates at high rate • All pixel hits are sent to periphery • Column based readout induces dead-time (during data transfer to periphery and column readout) • ATLAS solutions for higher rate • Development of regional architecture in FEI4 enabled by migration to a finer process

  18. FEI4 PIXEL REGION • FEI4 is organized in digital regions serving 4 analog pixels • Hits are stored locally during L1 latency • 5 ToT memories per pixel, 5 latency counters per region • Hits are not moved unless triggered • only 0.25% of hits are sent to periphery • Lower digital power consumption (6μW/pixel at IBL occupancy)

  19. FEI4: Pixel front end • Similar design of analog pixel in FEI3/FEI4 • Two-stage amplification • Clock is distributed to all digital pixel region • ToT counters within pixel digital region • ToT together with pixel address sent to periphery

  20. FEI4A: A result • FEI4 bump-bonded to planar and 3D sensors have been successfully operated in lab test, test beams and cosmic data taking • Tuned threshold dispersion ~30e • FEI4 low threshold operation (~700e) shows promising results with reasonable dispersion • Irradiation tests with bare chips show no effect on threshold dispersion and 20% increase in noise before tuning 103 Constant 849 Mean 3178 Sigma 403 Threshold tuning at 1400e 102 10 1 10-1 1500 2000 2500 3000 3500 4000 5000 Threshold [e] after tuning Constant 2865 Mean 3100 Sigma 26 103 102 10 1 10-1 2700 2900 3100 3300 3500 Threshold [e]

  21. Example 2: ATPIX65, next generation Atlas pixel readout prototype • To explore the capabilities of advanced CMOS processes to address future HEP needs (upgrades, SLHC, ) • To have a feel of what is the best way these processes should be used to maximize ROI. • To evaluate radiation hardness (mainly SEU and new damage mechanisms, if any!) • To keep abreast of the state of the art (if one can).

  22. Pixel region (2X2) a la FEI4 if implemented in 65nm • Region logic synthesized from FEI4 verilog. • Neither 100% complete nor verified. • Just to have an idea on what is possible • ~FEI4 AFE equivalent Pixel size=50X100 (?)

  23. FIE4 pixel region Vs Pix65nm region (assuming y=50u) FEI4 2X2 REGION (100X500) “FEI5” 2X2 REGION (100X200) If area to be kept the same as FEI4, about 4X more logic can be added => Substantial area reduction => Ultimately the width of a pixel will limited by practical considerations (power distribution) and not the number of transistors! => Room to add functionality

  24. Snapshot of submitted pixel array Config. Logic Config. Logic Analog FE Future Digital Region nXm pixels Analog FE Bump opening • 25 mm y cell pitch but 50mm bump y picth. • Power distribution will be major factor in the ultimate minimum dimensions • Bump mask not part of the submitted layout (same size as FEI4)

  25. ATPIX65A FEND BLOC DIAGRAM Passive RC: gate leakage limited TDAC (+/- 4b tuning) Preamp. 17fF Feeback cap. Variable “Rff” Inject Bloc Single to differential+ Comparator “preamp” Comparator • Uses only 65nm Transistors • 2mA to 25mA @ 1.2V

  26. ATPIX65A: Atlas Pixel prototype array 16 X 32 array 25m X 125m pixels Pixels with Added mimcaps (31,27,22,18) Pixels with Added sensors (row 11:31)

  27. Preliminary test results Chan 15/32 Qin: 2ke Preamp out Single to Diff. out Chip found to work as expected! VDD=1.2V I= 5mA per pixel (can be as low as 2mA)

  28. Chan 15/32 Qin: 2ke to 10ke- Qin=10ke-; 5IFF settings

  29. ATPIX65A: Noise and Threshold distribution Channels with caps or diodes

  30. ATPIX65A: ENC for some columns Channels with Diodes (3 types) . . . . Channels with mimcaps

  31. Fe55 spectrum as detected by one of the integrated sensors 2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?) For the experiment to agree with theory (for the 5.9KeV), injection cap has to be corrected by 15% . Still being reviewed! Noise artificially Limited 5154 KeV (theory; 5.9KeV?) 1040e- pulser injection ~3.7keV. Assuming Cinj to be nominal. Very preliminary! Work in progress! Chip2 high gain mode. Sensor@-8V

  32. Example 3: Apsel65 65nm pixel front end with MAPS Integrated sensor DNW-MAPS FFE Power consumption(mW) 20 6 ENC (e-) 38 200 Charge sensitivity(mV/fC) 725 40 Peaking time(ns) 300 25 Fast Front End for High resistivity pixels L. Gaioni et al. / Nuclear Instruments and Methods in Physics Research A 650 (2011) 163–168

  33. Example 4: Fast, rad-hard CMOS direct detectors for TEM 0.18 um CMOS K2 sensor (2010) 5m pixels • 16Mpix, 400 f/s Improved radiation tolerance Commercial product 0.35 um CMOS • TEAM2k(2009) • 9.5m pixels 4Mpix, 400 f/s HIPPIX (2011) 65nm proto • 0.35 um CMOS(2009) TEAM1k 1 Mpix B.Krieger, TNS 2011

  34. Example 4: HIPPO, a column-Parallel CCD readout (for X-ray imaging and muon collider applications) column-Parallel LBNL CCD Custom 65nm CMOS 35 e- @ 10 Mpix/s • Megapixel square sensor has ~1000 columns @ 50 μm pitch  need custom IC readout • No room for output amplifier need charge-sensitive readout • Ultimate applications require intensive DSP  advanced CMOS process • 65nm CMOS found to be the most adequate C. Grace, TNS 2011

  35. HIPPO prototype chip 4200 μm 16 Analog Front ends SERDES (480 Mb/s) 16 SHAs 4 ADCs 12b (80 Msps) HV input transistor to achieve the required noise level. Nominal transistor is too leaky!

  36. HIPPO results (mixed simulation and measurements) Preamp J.P. Walder, TNS 2011 ADC

  37. sensor Back SideMetal Super Contact Tier 1 (thinnedwafer) M1 M2 M3 M4 M5 M6 Bond Interface M6 M5 M4 M3 M2 M1 Tier 2 Super Contact ATLAS 3D EFFORT FE-I3 CMOS 250 nm 50 μm 400 μm FE-I4 CMOS 130 nm 50 μm 250 μm 50 μm 125 μm Tezzaron/chartered 2 tier Example FE-TC4 CMOS 130 nm 2 layers < 50 μm < 100 μm FE-X5-3D CMOS xx nm 3 layers • Achieves integration vertically • Optimized “tiers” • One of the “more than Moore” ways • Many challenges! A.Rozanov Atlas Upgrade Week 11/16/11

  38. Conclusions Unprecedented advances in IC technology are offering new ways to implement readout systems (for all kind of detector systems). New challenges seem to be more addressable with scaled down technologies. Future systems will require smaller geometries, lower power, higher level of processing, high radiation tolerance, lower cost per function, …etc Among the advantages of newer technologies are: Very high integration density Inherent high radiation tolerance A reasonable number of device types for extra design flexibility Availability of high quality passives A high number of metal levels Skewing the mix of functional blocs towards digital would result in a better area usage and chip yield. Not to mention flexibility (programmability) and Productivity (think advanced digital tools) A myriad of challenges related to ultra complex processes and ultra small devices are associated with these technologies. For some of these, mitigation techniques are readily available A unique challenge to the research community is perhaps the cost of these advanced processes (given the low volume usually involved). Common wisdom applies: for some applications plain old technologies would remain the optimal choice.

  39. Acknowledgements Many Thanks to all people whose work has been mentioned and to my colleagues at LBNL For their help. Please refer to the referenced work for more exciting details.

  40. Backup slides

  41. ATPIX65: ENC Vs Diode bias

  42. ATPIX65: ENC Vs Preamp Bias

  43. ATPIX65: ENC Vs IFF (feedback current)

  44. ATPIX65: Threshold Vs Preamp current

  45. ATPIX65: Threshold Vs feedback current

  46. Timewalk @Preamp current of 2ma and 0.2mA

  47. ATPIX65: Fe55 spectrum as detected by one of the integrated sensors ? ? (V) Very preliminary! Work in progress! Chip2 high gain mode. Sensor@0V

  48. Lower part of the Am241 spectrum as detected by one of the integrated sensors ? http://spie.org/x20060.xml?ArticleID=x20060 ? (V) Chip1 low gain mode Very preliminary! Work in progress! Low statistics

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