ECE 6371 Fundamental Hardware Design

1. ECE 6371Fundamental Hardware Design Ultra Fast Scheduler Yuhua Chen Sept 29th, 2009

2. Design and Implementation of An Ultra Fast Pipelined Wavelength Scheduler for Optical Burst Switching Yuhua Chen1 Jonathan S. Turner2 Zhi Zhai1 1 Department of Electrical and Computer Engineering University of Houston, Houston, Texas, USA 2 Department of Computer Science and Engineering Washington University in St. Louis, St. Louis, Missouri, USA

3. Outline • Introduction to Optical Burst Switching (OBS) • Ultra Fast Pipelined Scheduler Design • Summary

4. Optical Burst Switching (OBS) WDM Link OBS Edge Router OBS Core Router • Edge Router assembles and deassembles bursts. • Burst Header Cells (BHC) and data bursts are sent on separate channels. • OBS Core Router • Process BHC electronically. • Setup light path before burst arrival, tear down afterwards. • Data bursts stay in optical domain and pass through OBS routers transparently.

5. OBS Router Architecture Cell Switch Burst Processor E/O CS BP O/E BP E/O O/E BP E/O O/E BP O/E E/O Electronic Control Path Optical Data Path d: # of WDM links h: # of WDM channels Optical Switch WDM links BHC burst d h

6. Ultra Fast Optimal Wavelength Scheduling • The inefficiency of horizon scheduling is caused by large variation in offset. • If burst requests are processed in the burst arrival order, horizon scheduler can produce optimal wavelength schedules. • Constant Time Burst Resequencer (CTBR) uses hardware based Timing Wheel to resequence BHCs in O(1) time. • Combined with the O(1) runtime pipelined wavelength scheduler proposed in this paper, we can obtain an O(1) runtime Ultra Fast CTBR scheduler.

7. Constant Time Burst Resequencing • BHCs are appended to one of the time slots depending on burst arrival times. • BHCs are placed in the process list at ∆ time before the burst arrival times. • Adding and removing the BHCs are O(1) runtime operations.

8. BHC 35 55 burst 15 start time = BHC arrival time + offset = 15 + 55 = 70 end time = start time + length = 70 + 35 = 105 Horizon Scheduling Offset: 55 Length: 35 Channel chan1 chan0 40 60 70 time 105 • Horizon scheduling • Channel Horizon: latest time a channel is in use • Channel Selection: Choose the latest horizon before burst arrival • Channel Update: new horizon = burst end time

9. a: burst start time e: burst end time c: selected channel s: selection indicator (‘0’ or ‘1’) u: update indicator (‘0’ or ‘1’) Channel Status list Hi: Channel Horizon at stage i Ci: Channel Number at stage i H0≤H1≤…≤Hh-1 Ultra Fast Pipelined Wavelength Scheduler Burst request (a,e,c,s,u) Request Pipeline P0-Ph P0 P1 P2 P3 Ph-1 Ph u s … c e a Channel Status List H0 H1 H2 H3 Hh-1 … C0 C1 C2 C3 Ch-1

10. P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P6 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P8 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P5 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P0 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 u u u u u u u u u u u u u u u 0 0 0 0 0 0 0 0 0 s s s s s s s s s s s s s s s 0 0 0 0 0 0 0 0 0 c c c c c c c c c c c c c c c U U U U U U U U U e e e e e e e e e e e e e e e 66 66 66 50 54 54 54 54 54 a a a a a a a a a a a a a a a 40 40 40 32 18 18 18 18 18 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 1 79 79 79 79 79 79 79 79 79 79 79 79 79 79 79 H H H H H H H H H H H H H H H 66 58 66 66 58 66 58 58 58 58 58 66 58 58 58 54 38 38 54 54 54 47 47 54 50 38 50 38 38 38 58 47 47 58 58 58 50 50 47 47 47 58 47 58 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 34 16 34 34 34 16 16 0 16 34 34 16 16 34 16 47 47 25 47 34 47 25 47 34 47 25 34 47 34 25 50 50 34 34 34 47 50 34 50 50 47 38 50 38 34 0 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 1 1 0 1 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C C C C C C C C C C C C C C C C0 C1 C1 C1 C1 C0 C1 C0 C0 C1 C0 C1 C1 C1 C1 C0 U C7 U U C7 C2 U C0 C2 U C2 C2 C7 C7 U U C2 C2 C0 C0 C7 C0 C7 U C2 U C2 C7 C2 C2 C0 C7 C0 C0 C5 C2 C0 C2 C5 C0 C0 C1 C1 C1 C1 C5 C5 C1 C5 C1 C5 C5 C7 C5 C7 C5 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C6 C6 C2 C6 C6 C6 C6 C2 C2 C2 C6 C2 C6 C2 C2 C5 C5 C5 C6 C7 C5 C6 C7 C6 C5 C6 C5 C5 C7 C7 C7 C7 C6 C7 C5 C5 C0 C7 C0 C6 C7 C6 C6 C7 C6 50 54 66 54 50 54 66 50 50 66 54 66 66 54 50 54 50 50 66 66 54 54 50 50 54 66 66 Request 1: channel C7 Request 1: channel C7 Request 1: channel C7 Request 1: channel C7 Request 1: channel C7 40 32 18 40 18 40 18 18 40 32 32 18 18 40 18 32 40 18 32 32 40 32 32 18 32 40 40 Request 2: channel C0 Request 2: channel C0 Request 2: channel C0 Request 3: channel C2 Example of Multiple Requests Burst start time: 32 Burst end time: 50 Request Pipeline P0-P8 Channel Status List

11. Circuit Simulation Results • The proposed pipelined wavelength scheduler has been implemented in hardware using Verilog HDL. • The scheduler can process a burst request every two clock cycles. • If the clock frequency is 50 MHz (FPGA implementation), the processing time for each request is 40 ns (more than 50 times improvement over existing near optimal wavelength schedulers). • If the clock frequency is 500 MHz (130 nm ASIC), the processing time is 4 ns (more than 500 times improvement).

12. Summary • We have studied the negative impact of control path overloading on burst discard probability. • We have demonstrated an ultra fast pipelined wavelength scheduler design that can process a burst request every two clock cycles, regardless of the number of channels. • Depending on the target technology, the proposed wavelength scheduler can provide 50 to 500 times improvement over existing near optimal wavelength scheduler designs.