VLSI

1. VLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): [1] Mead, Conway, “Introduction to VLSI Systems”, Addison Wesley Publishing. [2] Glasser, Dobberpuhl, “The Design and Analysis of VLSI Circuits”, Addison Wesley Publishing. [3] Weste, Eshraghian, “Principles of CMOS VLSI Design”, Addison Wesley Publishing. [4] Shoji, “CMOS Digital Circuits Technology”, Prentice Hall.

2. Historical Overview • nMOS era: 1970-85 • Pass-transistor design • CMOS existed early but took off 1985 on • Domino CMOS, 1982 • NORA • DCVSL • CPL, DPL • DCVS-PG • SRPL • LEAP • SOI-CMOS Prof. V.G. Oklobdzija: High-Performance System Design

3. n-MOS Design Era 1970-85 LSI started with nMOS: • pass-transistor design experience: • Flourished at the beginning of the nMOS era (popularized by Mead-Conway book) • Allows high density layout and compact design style • Fast: outperforming gate based design • Low in power • Drawbacks: • Not compatible with existing design tools • Exhibiting testability and reliability problems Prof. V.G. Oklobdzija: High-Performance System Design

4. Review of CMOS Prof. Vojin G. Oklobdzija

5. CMOS Basics Prof. V.G. Oklobdzija: High-Performance System Design

6. CMOS Basics Prof. V.G. Oklobdzija: High-Performance System Design

7. CMOS Basics Prof. V.G. Oklobdzija: High-Performance System Design

8. CMOS Basics A complex path example: Prof. V.G. Oklobdzija: High-Performance System Design

9. CMOS Basics More complex blocks are realizable in CMOS Primitive gates: Prof. V.G. Oklobdzija: High-Performance System Design

10. CMOS Deficiencies: Muli-Input NOR function in CMOS is slow Various remedies: Prof. V.G. Oklobdzija: High-Performance System Design

11. CMOS Deficiencies and Remedies Prof. V.G. Oklobdzija: High-Performance System Design

12. CMOS Deficiencies and Remedies Prof. V.G. Oklobdzija: High-Performance System Design

13. CMOS Basic Inverter Transfer function: Logic voltage levels are VOH and VOL and VIL and VIH The inverter transfer function lie within the shaded region Prof. V.G. Oklobdzija: High-Performance System Design

14. CMOS Basic: Inverter Characteristic Leakage Currents Prof. V.G. Oklobdzija: High-Performance System Design

15. CMOS Basic: Inverter Characteristic Prof. V.G. Oklobdzija: High-Performance System Design

16. CMOS Basic: Inverter Characteristic Transistors during the transition Prof. V.G. Oklobdzija: High-Performance System Design

17. CMOS Basic: Inverter Switching Prof. V.G. Oklobdzija: High-Performance System Design

18. CMOS Basic: Power • During the static state there is no current • Current is only present during transistion: • Short circuit current (crow-bar current) • Charging and discharging of the output capacitor • Leakage Current Prof. V.G. Oklobdzija: High-Performance System Design

19. CMOS Basic: Power PCMOS=kCLV2DDfo This is an E=mc2 of low-power design There are three ways to control power: • Reducing Power-Supply Voltage (most effective !!) • Reducing the switching activity k (various ways) • Reducing CL (technology scaling etc.) • Reducing the required frequency of operation (?) Prof. V.G. Oklobdzija: High-Performance System Design

20. CMOS Basic: Delay • Which one of the three designs is the fastest ? • How can we find this out without simulation? Learn about Logical Effort ! Prof. V.G. Oklobdzija: High-Performance System Design

21. CMOS Basic: Delay Prof. V.G. Oklobdzija: High-Performance System Design

22. CMOS Basic: Delay Delay can be approximated with: RND7Cin1+RNORCin2+RND2Cout Prof. V.G. Oklobdzija: High-Performance System Design

23. CMOS Basic: Delay Delay of a signal path in CMOS logic is dependent on: • Fan-in of a gate • Represented as a resistance of the pull-up/down transistor path of the gate • Fan-out of a gate • Represented as a capacitive load at the output • Number of CMOS blocks in the path. • Wire delay connecting various blocks. Prof. V.G. Oklobdzija: High-Performance System Design

24. CMOS Basic: Delay Delay of a signal path in CMOS logic can be reduced by: • Making the transistors larger in order to minimize resistance of a pull-up/down path in the gate • Making the transistors smaller in order to minimize the capacitive load of each gate • Reducing the number of CMOS blocks in the path. • Bringing the blocks closer and/or choosing the less wire intensive topology. • Note that these requirements are often contradictory Prof. V.G. Oklobdzija: High-Performance System Design

25. CMOS Basic: Delay • How to estimate delay and critical timing in CMOS circuits ? • How to determine the proper transistor sizing in order to make a compromise with contradicting requirements ? • How to choose the right circuit topology ? The Answer: “Logical Effort” Prof. V.G. Oklobdzija: High-Performance System Design

26. Pass-Transistor Design Prof. V.G. Oklobdzija: High-Performance System Design

27. Pass-Transistor Design Another way of looking at Karnaugh Map: AND function Prof. V.G. Oklobdzija: High-Performance System Design

28. Pass-Transistor Design Two-variable function Prof. V.G. Oklobdzija: High-Performance System Design

29. Pass-Transistor Design “Threshold Voltage Drop” problem: Prof. V.G. Oklobdzija: High-Performance System Design

30. Pass-Transistor Design Solving the “Threshold Voltage Drop” problem in CMOS: Prof. V.G. Oklobdzija: High-Performance System Design

31. Pass-Transistor Design Function Generator Prof. V.G. Oklobdzija: High-Performance System Design

32. Pass-Transistor Design Full 1-bit Adder Prof. V.G. Oklobdzija: High-Performance System Design

33. Pass-Transistor Design Compact ALU Example (IBM PC/RT) Circ. 1984 Prof. V.G. Oklobdzija: High-Performance System Design

34. Prof. V.G. Oklobdzija: High-Performance System Design

35. Pass-Transistor Design Compact ALU Example (IBM PC/RT) Prof. V.G. Oklobdzija: High-Performance System Design

36. Using Pass-Transistor Design to Speed-up Addition Prof. V.G. Oklobdzija: High-Performance System Design