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Mixed-Mode BIST Based on Column Matching. Petr Fišer. Outline. Introduction to BIST State-of-the-art Methods Mixed-Mode BIST Column-Matching Method Experimental Results Conclusions Publications on Column-Matching Further Work. Introduction to BIST. Built-in Self-Test
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Mixed-Mode BIST Basedon Column Matching Petr Fišer
Outline • Introduction to BIST • State-of-the-art Methods • Mixed-Mode BIST • Column-Matching Method • Experimental Results • Conclusions • Publications on Column-Matching • Further Work
Introduction to BIST • Built-in Self-Test • Enables the device to test itself • Why (to) BIST? • With increasing integration density, the amount of manufacture faults is increasing • Thus, we have to test the chip • With increasing complexity of the design, it becomes impossible to test the chip externally • Thus, we HAVE to use BIST
Introduction to BIST The BIST Structure • Generate test patterns • Apply the patterns to the circuit • Evaluate the response
Introduction to BIST Two General Approaches to BIST • Test-per-scan Connect the CUT flip-flops into a scan chain Test the circuit serially • Test-per-clock Tests the circuit in parallel
Naive Methods • Exhaustive Testing • Generates all the 2n patterns • Extremely slow – impossible to use • Pseudo-Random Testing • Apply several pseudo-random patterns to the CUT • Complete fault coverage is not achieved • BOM-based BIST • Test patterns are stored in ROM • Big area overhead
State-of-the-art Methods • Reseeding • The pseudo-random test patterns are generated by LFSR • More LFSR seeds are applied • Weighted Pattern BIST • Change the probability of occurrence of 1s and 0s in the PR sequence • Bit-Fixing, Bit-Flipping, Row-matching • Modify the PR patterns by additional logic
Mixed-Mode BIST Combination of pseudo-random and deterministic BIST
Column-Matching • LFSR produces code words • These have to be transformed into deterministic patterns(computed by ATPG) => Output Decoder
Column-Matching Basic Principle • Try to reorder test patterns, so that most of the Decoder outputs will be implemented as wires – A Match • This will be accomplished when the particular columns of the LFSR and test matrix will be equal • Direct match – even the Switch logic is eliminated
Column-Matching Mixed-Mode BIST • Simulate first n LFSR patterns • Determine undetected faults • Compute a test for them (APTG) • Make a decoder producing test from LFSR patterns > n
Column-Matching Mixed-Mode BIST Two separate test phases • pseudorandom • and deterministic
Conclusions • Column-matching-based mixed-mode BIST method has been presented • Pseudo-random LFSR patterns are being transformed into deterministic vectors generated by ATPG by the Decoder • We try to match as many of the Decoder outputs as possible with its inputs, which yields no logic necessary to implement these outputs • Mixed-mode – two disjoint BIST phases introduced
Publications • Fišer, P. - Hlavička, J.: Column-Matching Based BIST Design Method. Proc. 7th IEEE Europian Test Workshop (ETW'02), Corfu (Greece), 26.-29.5.2002, pp. 15-16 • Fišer, P. - Hlavička, J. - Kubátová, H.: Column-Matching BIST Exploiting Test Don't-Cares. Proc. 8th IEEE Europian Test Workshop (ETW'03), Maastricht (The Netherlands), 25.-28.5.2003, pp. 215-216 • Fišer, P. - Kubátová, H.: An Efficient Mixed-Mode BIST Technique, Proc. 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2004 (DDECS'04), Tatranská Lomnica, SK, 18.-21.4.2004, pp. 227-230 • Fišer, P. - Kubátová, H.: Survey of the Algorithms in the Column-Matching BIST Method, Proc. 10th International On-Line Testing Symposium 2004 (IOLTS'04), Madeira, Portugal, 12.-14.7.2004, pp. 181 • Fišer, P. - Kubátová, H.: Pseudorandom Testability - Study of the Effect of the Generator Type, ECI'04, Herľany, SR, 22.-24.9.04 • Fišer, P. - Kubátová, H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST, BEC'04, Tallinn (Estonia), 3.-6.10.2004
Further Work • Use more sophisticated structures instead of a LFSR (cellular automata) • Adjust the width of a PRPG • Incorporate the ATPG into the design process – iterative test computation • Test-per-scan support • Partitioning of the CUT • Combine CM-BIST with other methods