Chapter 1 Part II. Basic Processing Unit Prof.Imteyaz Shahzad

1. ANJUMAN COLLEGE OF ENGINEERING & TECHNOLOGY Department of Computer Science & Engineering Chapter 1 Part II. Basic Processing Unit Prof.Imteyaz Shahzad

2. Syllabus: • UNIT I BASIC STRUCTURE OF COMPUTERS: Functional units, Von Neumann Architecture, Basic operational concepts, Bus structures Addressing modes, Subroutines: parameter passing, Instruction formats: Three- address Instructions, Two-address instructions, One- address instructions, Zero-address instructions. BASIC PROCESSING UNIT: Bus architecture, Execution of a complete instruction, sequencing of control signals, Hardwired control, Micro-programmed Control, microinstruction format. • UNIT II ARITHMETIC: Number representations and their operations, Addition and Subtraction with signed-magnitude, Design of Fast Adders, Array multiplier, Signed multiplication: Booth's Algorithm, Bit-pair recoding, Integer Division, Floating-point Arithmetic operations, guard bits and rounding. • UNIT III THE MEMORY SYSTEM: Various technologies used in memory design, higher order memory design, Memory hierarchy, Main memory, Auxiliary memory, Cache memory, cache optimization techniques ,Memory interleaving, Virtual memory, Address Space and Memory Space, Associative memory, Page table, Page Replacement

3. UNIT IV INPUT/OUTPUT ORGANIZATION: I/O mapped I/O and memory mapped I/O, Interrupts and Interrupts handling mechanisms, vectored interrupts, Synchronous vs. Asynchronous data transfer, Direct Memory Access COMPUTER PERIPHERALS: I/O devices such as magnetic disk, magnetic tape, CD-ROM systems. • UNIT V RISC philosophy pipelining, basic concepts in pipelining, delayed branch, branch prediction, data dependency, influence of pipelining on instruction set design, multiple execution units, performance considerations, • UNIT VI. Introduction to multiprocessors: Basic concepts in parallel processing, classification of parallel architectures. Vector Processing, Array Processor, Literature review of multi-core architecture

4. COURSE OUTCOMES: • Understand the basic components of a computer, including CPU, memories, and input/output, and their organization; understand the execution of complete instruction. • Perform mathematical operations on arithmetic and floating point numbers. • Understand the cost performance tradeoff in designing memory hierarchy and instruction sets. • Understand the I/O operation, interrupts, memory access by I/O and study different peripherals. • Understand the basic concept of pipeline execution of an operation. • Understand the basic concept of parallel processing and multi-core processor architecture.

5. Prerequisites What is? • Basic Operational Concept • Program Counter (PC) • Central Processing Unit (CPU) • Instruction Register (IR) • Memory Address Register (MAR) • Memory Data Register (MDR)

6. Fundamental Concepts • Processor fetches one instruction at a time and perform the operation specified. • Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. • Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). • Instruction Register (IR)

7. Executing an Instruction • Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR ← [[PC]] • Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC ← [PC] + 4 • Carry out the actions specified by the instruction in the IR (execution phase).

8. Single Bus Architecture Fig:refer from Carl Hamacher page 413

9. Execution of Instruction • Transfer a word of data from one processor register to another or to the ALU. • Perform an arithmetic or a logic operation and store the result in a processor register. • Fetch the contents of a given memory location and load them into a processor register. • Store a word of data from a processor register into a given memory location.

10. Internal processor b us R i in R i R i out Y in Y Constant 4 Select MUX A B ALU Z in Z Z out Fig.:Input and output gating for the registers Register Transfers Fig:refer from Carl Hamacher page 416

11. Performing an Arithmetic or Logic Operation • ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z. • First operand is always send to Register Y and Second is directly send to point B of ALU • What is the sequence of operations to add the contents of register R2 to those of R3 and store the result in R4? • R2out, Yin • R3out, SelectY, Add, Zin • Zout, R4in

12. Execution of a Complete Instruction • Add (R1), R2 • Fetch the instruction(Instruction Fetch Phase) • Fetch the first operand (the contents of the memory location Stored at R1) • Perform the addition • Load the result into R2

13. Execution of a Complete Instruction Add (R3), R1

14. Execution of Branch Instructions • A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction. • The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. • Conditional branch

15. Execution of Branch Instructions Step Action 1 PC , MAR , Read, Select4, Add, Z in in out 2 Z , PC , Y , WMF C out in in 3 MDR , IR out in 4 Offset-field-of-IR , Add, Z out in 5 Z , PC , End in out Figure Control sequence for an unconditional branch instruction.

16. Bus A Bus B Bus C Incrementer PC Re gister file Constant 4 MUX A ALU R B Instruction decoder IR MDR MAR Memory b us Address data lines lines Fig:Three Bus Organization of the datapath. Multiple-Bus Organization Fig:refer from Carl Hamacher page 424

17. Multiple-Bus Organization • Add R1, R2, R3 Step Action 1 PC , R=B, MAR , Read, IncPC out in 2 WMF C 3 MDR , R=B, IR in outB 4 R1 , R2 , SelectA, Add, R3 , End outA outB in Figure:Control sequence for the instruction. Add R1,R2,R3, for the three-bus organization