1 / 2

module fibonacci_calculator ( clk, reset_n , input_s, begin_fibo , fibo_out, done );

module fibonacci_calculator ( clk, reset_n , input_s, begin_fibo , fibo_out, done ); input clk; input reset_n; input [4:0] input_s; input begin_fibo; output [15:0] fibo_out; output done ; reg state;

kiley
Download Presentation

module fibonacci_calculator ( clk, reset_n , input_s, begin_fibo , fibo_out, done );

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. module fibonacci_calculator (clk, reset_n, input_s, begin_fibo, fibo_out, done); input clk; input reset_n; input [4:0] input_s; input begin_fibo; output [15:0] fibo_out; output done; reg state; reg [4:0] count; reg [15:0] R0; reg [15:0] R1; parameter IDLE = 1'b0; parameter COMPUTE = 1'b1; assign done = state & (count == 1); assign fibo_out = R0; always @(posedge clk or negedge reset_n) begin if (!reset_n) state <= IDLE; else case (state) IDLE: if (begin_fibo) begin count <= input_s; R0 <= 1; R1 <= 0; state <= COMPUTE; end COMPUTE: if (count > 1) begin count <= count - 1; R0 <= R0 + R1; R1 <= R0; end else state <= IDLE; endcase end endmodule

  2. reset_n clk module fibonacci_calculator clocked always statement assign statement 5 ==1 & Input_s count 0 1 done +1 5 1 0 1 R0 fibo_out + 16 0 0 1 R1 16 1 >1 0 1 state 0 0 1

More Related