Basic I/O Interfacing

1. WK 8 Basic I/O Interfacing

2. Objectives • Operation of basic I/O operations • Decode 8-, 16, and 32-bit addresses for enabling I/O ports • Handshaking for I/O operations • Interface and program the 82C55 PPI (programmable peripheral interface) • Using the 82C55 to connect LEDs, keyboards, etc. to the processor • Interface stepper and DC motors to the processor • Interface and program the 16550 programmable asynchronous serial interface adapter (UART) • Interface and program the 8254 programmable interval timer (PIT)

3. I/O Instructions • Two types: - Transfer data between the processor accumulator (AL, AX, EAX) register and I/O device: IN and OUT - Transfer string data between memory and I/O device directly: INSand OUTS (for processors above 8086) IN and OUT: • The IN instruction (I/O Read): Inputs data from an external I/O device to the accumulator. • The OUT instruction (I/O Write): Copies the contents of the accumulator out to an external I/O device. • The accumulator is: - AL (for 8-bit I/O), - AX (for 16-bit I/O), - EAX (for 32-bit I/O).

4. I/O Address • As with memory, I/O devices have I/O addresses (addresses for the I/O port) • Up to 64K I/O bytes can be addressed • The 16-bit port address appears on address bus bits A15-A0 This allows I/O devices at addresses 0000H-FFFFH • Two ways to specify an I/O port address: - An 8-bit immediate (fixed) address (specified as a byte in the instruction): e.g. IN AX, p8 ; Reads a word from port p8 0000H-00FFH (can only see the first 256 addresses) - A 16-bit address located in register DX (can be easily varied): e.g. OUT DX, AL; outputs the byte in AL to the port whose address is in DX 0000H-FFFFH (upto 16K addresses). i.e. high port addresses are accessible only through DX addressing DX 00FF Immediate

5. I/O Data widths • As with memory, I/O ports are also organized as bytes • A port can be 1, 2, or 4 bytes wide (not 8 bytes wide on the Pentium) Low Endian scheme: Low address byte contains low end (LS) part of data Port is 4 bytes wide 00F3H EAX 00F2H Port is 2 bytes wide 00F1H Port is 1 byte wide AX AL Port Address p8 00F0H LS byte

6. INS and OUTS I/O instructions • They address I/O port using register DX • Transfer string data between port and memory - INS: Moves string data to the Extra Segment;ES:DI - OUTS: Moves data from the Data Segment;DS:SI • As with other string instructions, DI and SI can be automatically incremented or decremented depending on the state of the DF (direction flag) bit • Data width of transfer specified by using INSB, INSW, and INSD for byte, word, and double word • Can be prefixed with REP to repeat the instruction for a number of times stored in CX

7. (Note corrections) Width of Transfer Determined by the ‘A’ register used I/O Read Width of Transfer Determined by the Instruction used DX DX DX No argument, DX by default I/O Write

8. Isolated vs. Memory Mapped • I/O can be either: - Isolated, or - Memory mapped • Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own address space for I/O ports (0000H-FFFFH)- isolated from the memory address space • Memory mapped I/O: uses memory reference instructions , e.g. MOV, and a region of the memory address map. So address space is shared between memory and I/O (used by only one of them) • Both techniques can be used with Intel processors • But most Intel-based systems e.g. the PC, use isolated I/O • Some other processors do not have dedicated I/O instructions and therefore use only memory-mapped I/O addressing, e.g. the PowerPC microprocessor (Macintosh computers)

9. Memory and I/O address Maps for the 8086/8088 I/O Port specified in DX, either explicitly or implicitly Memory: MOV • Isolated I/O • Using dedicated I/O • instructions e.g. IN, OUT I/O: IN 64 K I/O bytes 00FF Port specified immediately as a byte in the I/O instruction MOV Range of memory addresses assigned for I/O transfers b. Memory-mapped I/O Using ordinary memory transfer instructions e.g. MOV Memory

10. The PC I/O space • The PC I/O space mainly exists at locations below I/O port 0400H • Main board devices appear at addresses 0000H through 00FFH • Early ancillary I/O devices appear at I/O locations 0100H through 03FFH • Modern components appear at I/O locations above 0400H • The slide on the next page shows many of the I/O devices found in the personal computer

11. The PC I/O Address Space Processor communicates with and controls these peripherals through writing into/reading from their control registers accessed as I/O locations 03FF Must use 16-bitvariable I/O address in register DX Reserved for use by system components and ISA bus 0100 00FF Can Use either: - Fixed (immediate) 8-bit I/O address in instruction, p8 - Variable 16-bit I/O address in register DX Interval (8254) On Board Devices 0000 0000

12. IN (I/O Read) • The IN instruction primarily takes he following forms: IN AL,23H ;immediate IN AL,DX ;DX holds address IN AX,44H IN AX,DX IN EAX,2AH IN EAX,DX Data from the Input port addressed is put on the data bus for the processor to read into the A register Size of data transferred in each case?

13. OUT (I/O Write) • The OUT instruction primarily takes the following forms: OUT 23H,AL ;immediate OUT DX,AL ;DX holds port OUT 4CH,AX OUT DX,AX OUT 1EH,EAX OUT DX,EAX Data from the A register is put on the data bus for latching into the Output port addressed Size of data transferred in each case?

14. In embedded systems, most I/O is 8-bits • To write the data 00H into Output port 62H MOV AL,00H OUT 62H,AL or MOV AL,00H MOV DX,62H OUT DX,AL • To read a byte from Input port address 71H: • IN AL,71H • or • MOV DX,71H • IN AL,DX

15. Basic Input Port (for I/O Reads) • The basic input port connects an external set of bits to the mP data bus whenever the mP executes the correct IN instruction with the correct I/O port address • External device puts data on the mP data bus  Must include a 3-state (Tri-State) buffer to limit access to the processor data bus to the duration of executing the I/O instruction only

16. Basic 8-bit Input Interface: Reads the status of 8 toggle Switches (a byte read) Pull-up Resistors To mP Gate Outputs: Normally Hi-Z Unless device is Selected (both G1 and G2 low) 0 1 Toggle switches 3-state buffer The SEL signal is generated (active low) By decoding: - The address for the I/O port - The I/O READ operation Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces

17. Basic Output Port (for I/O Writes) • The basic output port writes data from the mP data bus to an output port whenever the mP executes the correct OUT instruction with the correct I/O port address • Must latch the processor data put on the bus during the I/O instruction to make it available indefinitely for the port • No need for 3-state (Tri-State) buffers as the data bus is at the input side of the latch

18. Basic 8-bit Output Interface: Controls 8 LEDs (1: OFF, 0: ON) Circuit can be expanded for 16-bit (word) or 32-bit (DWord) interfaces From mP Edge-triggered latch OE No HiZ. O/P always enabled Data is latched and remains here until the next OUT instruction to this port is executed The SEL is generated (for + ive edge triggering) by decoding: - The address for the I/O port - The I/O WRITE operation

19. Parallel Port • The parallel port is an example of interfacing slow devices, e.g. a printer, to the processor • A printer can print say 100’s of characters per sec (CPS), but the processor can output as many as 1000’s of CPS • To achieve ‘flow control’ and proper operation we use a technique called handshaking • Handshaking regulates the flow of data from the processor to a slower peripheral device to ensure correct operation

20. Computer (parallel port) has • a 25-pin DB25 connector • - Printer has a 36-pin Centronics • connector Printer side Computer side Computer Printer Computer Printer Strobe Data Into Printer (STB) Data 8-bit Character data Processor polls ‘Busy’ to see if BUSY = 0 (printer not busy), so processor can send the data for next character

21. BUSY is the I/O address of the input port receiving the BUSY signal from printer BUSY = 1: printer is busy printing- do not send a new character BUSY = 0: printer is not busy - send a new character now ;An assembly language procedure that prints the ASCII data byte in register BL. PRINT PROC NEAR .REPEAT ;Poll the busy line until it goes low IN AL,BUSY ;READ the port having the BUSY input TEST AL,BUSY_BIT_MASK ;test if the Busy bit in the data read is 0 ;BUSY_BIT is a mask defining the position ;of the BUSY bit in the port .UNTIL ZERO ;End waiting loop if the ZERO flag is set MOV AL,BL ;Yes!...move character data to AL OUT PRINTER,AL ;and output it to printer- ;PRINTER is address of the printer port ;This also generates the #STB pulse RET PRINT ENDP Loop repeatedly reads BUSY & checks if it is low Here BUSY = 0! So output data to Printer! For example, if Busy goes on bit 4 of the BUSY port, BUSY_BIT_MASK will be: 00001000 and the instruction TEST AL, BUSY_BIT_MASK will AND AL with the bit pattern 00001000. The result will be 0 only if the BUSY Input is 0, setting the ZERO flag and ending the waiting (handshake Loop)

22. Interfacing When connecting external input and output devices to the processor, we must take into account the DC characteristics and drive capabilities of the mP pins, see Chapter 9 (Fan-out considerations For outputs before) mP Output Devices, e.g. LEDs Input Devices, e.g. Switches mP Input mP Output Source Sink Source Sink

23. TTL Input to mP Input Devices: The Switch = 5 V • The most basic input device • Switches are passive- do not produce a voltage, easily present a logic 0 to an I/P by grounding it. • To make a switch TTL compatible, a pullup resistor is used as shown. The value should be between 1K and 27K W. • Why not, say, 400 K W? • Switches bounce… and this is often undesirable. Iin, High (Single Pole Single Throw) The pullup resistor does the conditioning required to allow the switch to produce a TTL compatible input to the processor Here, processor senses the switch effect directly- hence bouncing is a problem, especially if input Is used as a clock Wrong switch State Can be read Here ! Final Posn Initial Posn

24. TTL Input to mP The switch Bouncing Problem • Switch contacts bounce mechanically before it finally settles in the new position • With the simple arrangement shown, bounces can lead to the wrong input being read by the processor • The effect of switch bounces can be removed either:  by Software, discussed later: Simply wait a little before reading the new switch status  by hardware • Hardware solutions increase circuit cost and complexity

25. Switch De-bouncing Circuits To Processor To Processor • Simpler, cheaper circuit • (inverters not NANDs) • - No pullup resistors required 1 1 Bouncing causes  No Change from New state • Processor now senses the output of a bistable flip flop (FF) • (with memory) controlled by the switch (not the switch directly as before) • Instantaneous change in the switch position causes a permanent • change in the FF output to the processor • A little bounce from the new position will not cause the FF to change state as • it remembers (through the feedback) the latest output before the bounce

26. Output Devices: The LED • LED diodes are used in many systems as indicators and as sources of infrared beams • LED must be forward biased to conduct and emit light • When conducting, a typical (Red, Green, or Yellow) LED passes a current of about 10 mA with a voltage drop Vdiode 1.65 V (1.5 V - 2 V in practice) • A Blue, White, or UltraBright LED passes more current at a larger voltage drop, e.g. 30 mA @ 2.5 V. + 1.65 V _ 10 mA A bit of electronics!

27. Interfacing the LED directly to a TTL O/P • 10 mA currents can be easily sunk by a TTL output at the low state (0) (A standard 74 TTL O/P sinks up to 16 mA – lower values for lower power series e.g. 74LS sinks only 4 mA) • V out, low  0.1 V • V diode  1.65 V • To ensure I = 10 mA, R should be = +5V + V diode _ I min = 10 mA R V out LED ON indicates 1 or 0 at Input? Nearest standard resistor value

28. Interfacing the LED through a transistor Common Emitter • If diode takes current > TTL sink current at the low state: Use a transistor to connect the LED • Transistor current gain (b= Ic/Ib  100) reduces current requirement from the TTL circuit (e.g. the mP or the buffer IC) • Ib = Ic/100 = 10mA/100 0.1 mA • Rc calculated as before, similar value • Rb should not be larger than: + 1.65 V _ Ic = 10 mA Ib = 0.1 mA c b (TTL) e 0.1V Rb 0.7V (Transistor Is saturated) Transistor: b = Base e = Emitter c = Collector Use minimum gain value specified (worst case condition) Nearest standard resistor value

29. Driving larger currents and voltages; e.g. DC motors, mechanical relays, etc. • Large current loads such as motors or large relays require a Darlington pair in place of the transistor driver • Two transistor gains in cascade, (b = b1 b2), so smaller base currents from TTL for large load currents • Can use 12 V or higher supply • Select a transistor that meets both the voltage and current requirements for the load • The diode is used to prevent the transistor from being destroyed by the inductive kickback current that appears when the field collapses suddenly in the coil Current can not change instantly through an inductor. If it suddenly drops from I1 to 0, a negative current - I1 is generated which gradually decays to 0. The diode provides a safe path for this current away from the transistor 12 V DC Motor Ic = 1 A Rb (TTL) 0.7V 0.7V Diode off In normal operation 1A/(7000)=0.143 mA b = b1 b2

30. WK 9 Port Address Decoders • As with memory addresses, port addresses must also be decoded to select an I/O device for a particular port number. • Memory mapped I/O is identical to memory access (with IO/#M = 0) • Will consider here only isolated I/O (using dedicated instructions: IN, OUT, etc.) • Most embedded systems use only fixed I/O addressing: - i.e. Only the least significant eight address bits A7-A0 are decoded. Limits number of I/O ports to 256 (enough) • PC systems used fixed/variable I/O addressing: - All 16-bits of the I/O address A15-A0 are decoded, allowing the use of up to 64K ports • Decoding is simpler than for memory- smaller # of address lines • Isolated I/O transfers are activated using (depending on processor and mode): - IO/#M = 1, M/#IO = 0, #IORC, #IOWC, #RD, #WR, W/#R

31. Address Decoding for 8 I/O Ports: F0 to F7for the 8088 using 8-bit I/O address a. Using a Decoder IC Decoder O/Ps Decoder I/Ps X X X 0 1 1 1 1 X X X 1 0 1 1 1 LS part (Select port on decoder) To ‘Enable’ Inputs on the 8 I/O ports MS part (Enable decoder) A7 …....A0 3-to-8 Decoder 11110000 = F0 1st 11110001 = F1 2nd ……………………. 11110111 = F7 7th Address from mP Note: #IO/M decoding should be added

32. A7 …....A0 11110000 = F0 1st 11110001 = F1 2nd ……………………. 11110111 = F7 7th b. Using a PLD library ieee; use ieee.std_logic_1164.all; entity DECODER_11_11 is port ( A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_11 is begin D0 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0 ); D1 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0 ); D2 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0 ); D3 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0 ); D4 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0 ); D5 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0 ); D6 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0 ); D7 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0 ); end V1; Outputs are active low I/O control not decoded

33. Address Decoding for 8 I/O Ports:for the 8088 with 16-bit I/O address library ieee; use ieee.std_logic_1164.all; entity DECODER_11_12 is port ( Z, A12, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_12 is begin D0 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and not A1 and not A0 ); D1 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and not A1 and A0 ); D2 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and A1 and not A0 ); D3 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and not A2 and A1 and A0 ); D4 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and not A1 and not A0 ); D5 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and not A1 and A0 ); D6 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and A1 and not A0 ); D7 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and A4 and A3 and A2 and A1 and A0 ); end V1; Note: I/O control not decoded I/P Z = not (A15 & A14 & A13 & A11) 16 I/Ps Check: #(1110111111111011) = #EFFBH

34. Same with memory banks, we have multiple I/O byte banks (each 1 byte) For processors with a 16-bit data bus: 2 banks (for low and high bytes) 64K 8-byte I/O ports  32K 16-bit ports (decoded using most significant 15 bits of the 16-bit I/O address) Which byte in the port is determined by the LSB (A0) and the #BHE: For I/O writes, as with memory, use separate strobe signals (e.g. #BLE or #BHE) for the separate byte ports For reads, normally no action is required as processor reads the byte it wants. This is OK assuming the port responds correctly to the read command from the processor 16-bit Wide I/O: 8086,286, 386SX 64K Byte Ports 32K Word Ports LS byte port MS byte port 16-bit (Word) port: Port # starts with A1 not A0 (15 lines  215 = 32K 16-bit ports) A0 goes through 1 and 0  it is a don’t care

35. Byte Selection in a 16-bit port Enabled with #BHE Enabled with #A0

36. Byte (bank) selection for Writes only… i.e. for OUT ports only 16-bit Output Port which allows the processor to write into either or both its two separate bytes mP Data Bus A7 A1 40H = 0100 0000 (mostly zeros  use OR function) D0 = A7+#A6+A5+A4+A3+A2+A1+A0+ #IOWC I/O Write Start with A1 Low Byte Port Strobe mP Data In Similar to memory, Data is written into port at the rising edge of #WR Width Determine by Narrowest Signal Which is? This part Is the same For both byte ports Strobe mPData In 41H = 0100 0001 High Byte Port D1 = A7+#A6+A5+A4+A3+A2+A1+ #BHE + #IOWC Output always enabled: Tri-state feature is not utilized Not required for output ports D8 Start with A1

37. library ieee; use ieee.std_logic_1164.all; entity DECODER_11_14 is port ( BHE, IOWC, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1: out STD_LOGIC ); end; architecture V1 of DECODER_11_14 is begin D0 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or A0; D1 <= A7 or not A6 or A5 or A4 or A3 or A2 or A1 or IOWC or BHE; end V1;

38. 16-bit Input Port: No use of BHE or A0 (Processor knows which byte it wants) Buffers must be Tri-State Because their outputs connect to the Processor data bus! mP Data Bus No A0 or BHE Dropped A0 I/O Read Common Strobe for both byte ports (No byte selection for READs) Allow External Data In (No latching) 7-bit address 7-bit address lines 27 = 128 x 2-byte ports (= 256 byte ports) Simple buffers not latches- Data is available For long time at I/P

39. library ieee; use ieee.std_logic_1164.all; entity DECODER_11_15 is port ( IORC, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_15 is begin D0 <= IORC or A7 or not A6 or not A5 or A4 or A3 or not A2 or A1; end V1; A0 1 1 0 0 1 0 0 0 1 Lower Byte: 64H Higher byte: 65H The lowest 8-bit address (64H) is used by the software to address this 2-byte port for all READs from its two bytes

40. 32-bit Wide I/O, e.g. for 80486 • The only difference between 16-bit wide I/O and 32-bit wide I/O is that 32-bit wide I/O consists of 4 side-by-side 8-bit ports instead of 2. • Same as with memory interface: for each doubling of the number of byte ports connected to the data bus  drop one more of the LS address bits • So with 80486 we (32-bit data bus) we drop A0 and A1 • Next slide illustrates a 32-bit wide input port that decodes only 6 bits of address.

42. library ieee; use ieee.std_logic_1164.all; entity DECODER_11_16 is port ( IORC, A7, A6, A5, A4, A3, A2: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_16 is begin D0 <= IORC or A7 or not A6 or not A5 or not A4 or A3 or A2; end V1; A1 A0 (not decoded) 0 0 0 1 1 1 0 0 70H 0 1 Determine the 4 addresses of the four byte ports and Verify you get addresses given on the previous slide 1 0 1 1 The lowest 8-bit address (70H) is used by the software to address this 4-byte port

43. I/O for the Pentium • Although the Pentium has a 64-bit data bus, only memory transfers use it • I/O instructions support a maximum of 32 bit transfers, i.e. over a max of 4-byte ports (EAX is 32 bits!) • Pentium has 8 byte enable signals BE0, …, BE7 to allow selecting the byte to be written into a memory bank • For I/O, we will use them to select which I/O byte bank to write into for output ports • Which bank to read from an input ports is left to the processor (no hardware bank selection for READS) • The bank number is determined by the LS 3 bits of the byte address (replaced by the 8 BEi signals) Pentium 8 byte banks. I/O uses a max of only 4 banks at a time XX111 XX110 XX101 XX100 XX011 XX010 XX001 XX000

44. I/O for the Pentium Still 16-bit address for I/O • Examples: • Byte port 0034H: • 00110100  Bank 4 • (i.e. Use BE4) • 2-Byte port 005CH-005DH: • 01011100-01011101  4,5 • (Use BE4, BE5) • - 4-byte port 0104H-0107H: • ….0100-….0111  4,5,6,7 • (Use BE4,BE5,BE6,BE7) XX111 XX110 XX101 XX100 XX011 XX010 Invalid 32-bit port XX001 XX000 Two valid 32-bit ports (22 bytes): Moving within the port changes only the 2 LSBs of the address Any bank can be a byte port Four valid 16-bit ports (21 bytes): Moving within the port changes only the LSB of the address Invalid 16-bit port

45. Byte 0 Byte 1 2-byte Output (Write) port for the Pentium at addresses 2000H and 2001H: ….0000-….0001  Banks 0,1 (i.e. use BE0, BE1) Determine which BEs to use from LS 3-bits of address A2-A0 A2-A0 Dropped Bank 0 (BE0) Outside World mP Data Bus Bank 1 (BE1)

46. library ieee; use ieee.std_logic_1164.all; entity DECODER_11_17 is port ( MIO, BE0, BE1, WR, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3: in STD_LOGIC; D0, D1: out STD_LOGIC ); end; architecture V1 of DECODER_11_17 is begin D0 <= MIO or BE0 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3; D1 <= MIO or BE1 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7 or A6 or A5 or A4 or A3; end V1;

47. The 82C55 PPI PPI = Programmable Peripheral Interface • The 8255 allows the microprocessor to communicate with the outside world through three programmable 8-bit wide I/O ports • The PC uses a few 82C55 (in the chip set) to control the keyboard, speaker, and parallel port • The 8255 PPI is available in DIP or surface mount forms • Also implemented as functions within modern interface chip sets

48. 3 programmable 8-bit I/O ports: A, B, C Similar to a 4-byte RAM 2 Groups 12-bit groups A, B A Data Bus Port A + Upper half of C = Group A (12 bits) 2-bit Address I/P (select port or Command register for Read or Write) B Read/Write Control Port B + lower half of C = Group B (12 bits) CS Input (low) • On the PC: Two 82C55s • One 82C55 occupies • 4 I/O ports 60H-63H: • Handling Keyboard, timer, • speaker, etc. • One 82C55 occupies • 4 I/O ports 378H-37BH • Parallel printer port C RESET initializes the PPI to operate in mode 0 & all 3 ports as inputs at power up. With all ports as input ports, this avoids damage to the device at Power up 82C55 DIP Version

49. B

50. I/O Port Assignments • Group A is Port A and upper ½ of Port C (PC7-PC4). • Group B is Port B and lower ½ of Port C (PC3-PC0). Writing into this register programs the various ports to operate in various modes and be used as either inputs or outputs