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High speed signal transmission. Jan Buytaert. Topics. Electrical standards: CML,LVDS, SLVS Equalization . Testbench of a readout slice. Vacuum feed - throughs . Cable choice ( development ). ‘ Current scenario’.
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High speed signal transmission Jan Buytaert
Topics • Electrical standards: CML,LVDS, SLVS • Equalization. • Testbench of a readout slice. • Vacuum feed-throughs. • Cablechoice (development)
‘Current scenario’ • There is consensus in the VELO group to have the electro/optical transition outside the vacuum vessel. • The ‘Building block’ for modules willbe 6 VELOpixasics. • Eachasicswill have ~4 high speed outputs (at ~ 4 Gbit/s). • Total number of datalinks per ‘building block’ = 24. • Total number of datalinks in system = (23 x 4) x 24 = 2208.
CML (current mode logic) • + popular in electrichigh speed signaling on pcb . (laser drivers, serdes) • + simple output stage. • +compatible withlow CMOS supply voltages (e.g. 1.2V) • + voltage swing canbecontrolled by current source (thus power consumption !) . • asymmetric drive strength for rising/fallingedges. • not fullydifferential transmission (the mirrorcurrentiscarried by the shield, not by the second conductor...) • This is OK for pcb short traces, but lessadapted to differentialcable transmission. • + Can be double-terminatedwhenac-coupled. i or 0 0 or i i
LVDS. • + popularin electrichigh speed signaling on cable. • - More complex output stage. : 3mA currentsteering • - not compatible withlow CMOS supply voltages (e.g. 1.2V) • Voltage swing 2x300mV on 100 ohm, common mode =1.2V • + symmetricdrive strength for rising/fallingedges. • + fullydifferential transmission (the mirrorcurrentiscarried by the second conductor, the shielddoes not carry transientcurrents.) • + This is OK for pcb and differentialcable transmission. • +‘Floating’ termination. • + proven to be an excellent digital I/O standard on sensitive analogasics ! i Zdiff + i or -i i
sLVS(scalablelow voltage signalling) • + popular in electrichigh speed signaling for imaging and portables. • + used for e-links in GBT project (320Mbit/s). • + compatible withlow CMOS supplyvoltages ( common mode = 200mV) • + voltage swing couldbecontrolled by current source 0.5mA to 2mA (thus power consumption !) . • differential voltage swing on 100 ohm : 100mV to 400mV . • + symmetricdrive strength for rising/fallingedges. • + fullydifferential transmission (the return currentiscarried by the second conductor, the shielddoes not carry transientcurrents.) • This is OK for pcb and differentialcable transmission.
Equalisation. • Will mostlikelyberequired to transmit 5Gbit/s over 2m low mass cables(highdistortion) and connectors. • Commercial driver : ONET1101L from TI ? • 11.3 GbpsVCSEL Laser Diode Driver. • Programmable modulation and biascurrent. • Programmable input equalizer. • used in ‘versatile linkproject’ as commercial laser driver. • Radiation dose and SEU tolerant ??? Wecouldtry to qualify ? • Includein VELOpix ? • Seepresentation by BRUCO (+NIKHEF) on high speed link. Equalization by PWM technique.
Testbench of a readoutslide. • Propose to startfrom the BERT (bit error rate tester) developedat CERN by ‘versatile linkproject’. FPGA based. • Experimentwithlow mass cables and connectors, laser drivers,etc … • Shouldfollowclosely the ‘ATLAS-CMS optical transmission working group’ (e.g. Atlas liquid argon upgrade verysimilar to VELO !) • Sincewe have 24 links per VELOpix module, EMI/EMS (crosstalk) isvery important.