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Investigating latchup in the PXL detector

Investigating latchup in the PXL detector. Outline: What is latchup? the consequences and sources of latchup techniques to reduce latchup sensitivity Other single event effects Latchup tests at BNL Latchup tests at 88” cyclotron Latchup tests at STAR Radiation environment at STAR

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Investigating latchup in the PXL detector

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  1. Investigating latchup in the PXL detector Outline: What is latchup? the consequences and sources of latchup techniques to reduce latchup sensitivity Other single event effects Latchup tests at BNL Latchup tests at 88” cyclotron Latchup tests at STAR Radiation environment at STAR Summary

  2. What is latchup • Latch-up – inadvertent creation of a low-impedance path, typically, but not only, between the power supply rails of an electronic component that triggers a thyristor-like parasitic structure, which acts as a short circuit. • sustainable condition as long as the holding current can be delivered • To remove latchup, the circuit needs to be powered down Consequences: • damage to bond wires • localized melting of metallization on the die due to localized overheating CMOS device with parasitic bipolar transistors

  3. Sources of latchup • Supply voltages exceeding the absolute maximum ratings.  • input/output pin voltage exceeding either supply rail by more than a diode drop.  • incorrect power sequencing. • Various spikes and transients • Energetic particles (Single Event Latchup - SEL) Increasing density and circuit complexity in modern VLSI CMOS devices makes them more susceptible to latchup.

  4. www.analog.com www.ti.com www.ti.com Techniques to minimize latchup sensitivity • Increasing PMOS-NMOS spacing • Guard rings to form additional collectors for the parasitic transistors • Clamping diodes, current limiting resistors • CMOS processes: • Epitaxial layer instead of bulk CMOS • Retrograde well • Oxide trenches between the NMOS and PMOS devices

  5. What do we do for the PXL detector? We know that latchup can happen in MAPS (see later slides) • At IPHC • On-going redesign of the standard digital cells for increased spacing between NMOS and PMOS transistors • At LBL • Building power supply modules for PXL ladders with over-current monitoring and automated shut down

  6. Other Single Event Effects (SEE) • Single event upset (SEU) • Bit-flips in memory chips and microprocessors • Other effects: • a glitch, or a temporary change-of-state of the output in combinatorial digital circuits • Spurious pulse in analog electronics

  7. Latchup tests at TVDG at BNL Ion beam Test chamber Test chamber Device under test (DUT) Power supplies + current monitoring

  8. Latchup cross section of various MAPS prototypes LET – Linear energy transfer onset of SEU

  9. LU and SEU at 88” • Test chamber • Readout system • Test PCB • Milled down IC package

  10. Latchup tests at 88” cyclotron Test results: Mimosa26, LU_test_structures, ADC Preliminary results, raw data Single counts

  11. Summary of heavy ion tests • Estimated the onset energy for latchup (let’s remember that 1.6 MeV cm2/mg  1000 MIP) • Measured latchup cross-sections • However in STAR we don’t expect to see such heavy ions • In STAR we can not generate the amount of required LET based on the same energy loss mechanisms (primary ionization) • We expect that the latchup will be dominated by inelastic nuclear collisions from particles with charge 1

  12. Latchup tests at STAR • 2 x Mimosa26 chips • VDA, VDD, VMEM • 1 voltage regulator Mimosa26 – predecessor of PXL sensor (Ultimate) includes on-chip zero suppression Mimosa 26 – ½ reticle size, memory 4 × 600 × 16 bits PXL sensor – full reticle size, memory 4 × 2048 × 16 bits

  13. (500 GeV p+p) (200 GeV Au+Au) (200 GeV Au+Au) latchup (?) in STAR • Monitoring since 13 April 2011, ~12:00 pm (EDT) • Registered events: • 17 April 2011, ~9:00 pm (EDT) – MEM1 • 6 May 2011, ~1:08 am (EDT) – VDD2 • 24 May 2011, ~10:03 am (EDT) – VDD1

  14. latchup in STAR • Assuming that the mechanisms behind the observed event rates scale with the charged particle density, • and therefore, with the integrated dose (next 2 slides) • We can try to make predictions for latchup rates in the PXL detector

  15. PXL radiation environment - results from Howard Matis

  16. BLM measurements by H.M.

  17. Implications • 3 events per 7 weeks per sensor @ 5cm • ~1 event per detector per hour × higher luminosity • ~5 events per hour • PXL goes busy while we reset our detector • ~1s per reset • This would increase the PXL dead time by 0.14% • But we also need • Preferably more statistics • Corrections for the integrated luminosity • Corrections for sensor layout Extremely simple calculations, not a real prediction • Latchup @ reasonable rates => not a problem

  18. Backup slides

  19. SEU

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