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Report on SVD2 L0/L1 M. Hazumi and T. Nakadaira Mar. 6, 2003 Belle SVD meeting

Report on SVD2 L0/L1 M. Hazumi and T. Nakadaira Mar. 6, 2003 Belle SVD meeting. TA tuning test with 1/10 system Other activities Schedule. NIM logic. TTM2. trigger scinti. D O C K. PMT. ADCTF. L0T. ladder. PMT. VME. VME. beta source.

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Report on SVD2 L0/L1 M. Hazumi and T. Nakadaira Mar. 6, 2003 Belle SVD meeting

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  1. Report on SVD2 L0/L1M. Hazumi and T. NakadairaMar. 6, 2003Belle SVD meeting • TA tuning test with 1/10 system • Other activities • Schedule

  2. NIM logic TTM2 trigger scinti. D O C K PMT ADCTF L0T ladder PMT VME VME beta source 1-page summary of TA tuning test results(details in the following slides) • Preparation of 1/10 test system for TA tuning completed • trigger with scintillators, take both TA hits and VA outputs as data • Tuning (parameter scan) carried out with b source signal • Test_on = 0: no additional noise from test_pulse input (more stable) • Efficiency improved by changing <trimDAC> and globalTh • TA hit efficiency: 47%  87% • Tuning for Ifsf and Sbi in progress • Life is much easier for Tp=300ns ! • TA hit efficiency: 99% only by adjusting <trimDAC>

  3. Procedure to study TA efficiency • Find a cluster with VA information • Find a VA1TA chip that corresponds to the VA cluster • Check TA hit from that chip Results on the p-side (for Z trigger) are shown today

  4. noise b source all clusters Tp=75ns <trimDAC> = 1 globalTh = 4400e- Result before TA tuning Definitions TA hit efficiency = #(w/ TA hits) #(all clusters) for Cluster Energy (CE) >60 ADC counts (~0.5 MIP) TA noise hit fraction= #(w/ TA hist) #(all clusters) for 10 < CE < 40 TA hit efficiency = (47  1)% TA noise hit fraction = ( 3  1)% w/ TA hits Threshold curve #(w/ TA hits) #(all clusters) for each bin

  5. <trimDAC> tuning (for Tp=75ns) Efficiency improved while keeping the similar noise level

  6. Tp=75ns <trimDAC> = 2/16 globalTh = 4400e- Result after <trimDAC> tuning Definitions TA hit efficiency = #(w/ TA hits) #(all clusters) for Cluster Energy (CE) >60 ADC counts (~0.5 MIP) TA noise hit fraction= #(w/ TA hist) #(all clusters) for 10 < CE < 40 TA hit efficiency = (77  1)% TA noise hit fraction = ( 5  1)% Threshold curve #(w/ TA hits) #(all clusters) for each bin

  7. globalTh tuning (Tp=75ns) Efficiency improved: noisy if globalTh=2000e- or 2200e-

  8. Tp=75ns <trimDAC> = 2/16 globalTh = 2400e- Result after globalTh tuning Definitions TA hit efficiency = #(w/ TA hits) #(all clusters) for Cluster Energy (CE) >60 ADC counts (~0.5 MIP) TA noise hit fraction= #(w/ TA hist) #(all clusters) for 10 < CE < 40 TA hit efficiency = (87  1)% TA noise hit fraction = ( 3  1)% Threshold curve #(w/ TA hits) #(all clusters) for each bin

  9. Remark on the threshold curve 9000e- actual TA threshold 8000e- dE/dx(ADC count) strip ID If the actual TA threshold is 10000e-, TA is not fired by this cluster, although the cluster energy (17000e-) is large (~1MIP). Additional effect: difference between test pulse and b source

  10. Further tests in progress.. • Ifsf tuning • Sbi tuning • both were found to be effective to decrease the threshold (privious tests by Kawai-san) • n-side (rphi side) investigation • Note that the tests on the p-side were carried out with both p-side and n-side TAs ON (n-side <trimDAC>=1).

  11. <trimDAC> tuning (for Tp=300ns) Efficiencies are higher than those for Tp=75ns

  12. Tp=300ns <trimDAC> = 8/16 globalTh = 4400e- Life is much easier with Tp=300ns ! Definitions TA hit efficiency = #(w/ TA hits) #(all clusters) for Cluster Energy (CE) >60 ADC counts (~0.5 MIP) TA noise hit fraction= #(w/ TA hist) #(all clusters) for 10 < CE < 40 TA hit efficiency = (99  1)% TA noise hit fraction = ( 3  1)% Threshold curve #(w/ TA hits) #(all clusters) for each bin

  13. Discussion • Tp=300ns much better than Tp=75ns • Encouraging ! L1 trigger will be OK if we take this option ! • Consistent with IDEAS test results (http://belle.kek.jp/~svd2/va1ta/va1ta_test05.pdf) • L0 latency (max.) = 835ns; Is this acceptable ? • Eff.=87% for Tp=75ns; adequate ? • need simulation study • simple estimation  91.5% for 3-out-of-4 logic • Several possible options • Tp=300ns for Z trigger for L1, Tp=75ns for rphi for L0 • Tp=300ns with L0 latency=835ns • ... • The decision depends on the actual condition. • Test_on=0 “seems” more stable

  14. Other activities • Specification of L0/L1 system on www • http://belle.kek.jp/~svd2/trigger/TA/doc/svd2L0L1Spec.pdf • based on discussions with Iwasaki-san (CDC trig. expert) • will be updated by putting more information • will be explained at the progress meeting on Mar.20 • Preparation of TA calib. scheme for the full system in progress (Ishino et al.) • Mikami/Ushiroda started L0 firmware design work • TA trigger web page now available • http://belle.kek.jp/~svd2/trigger/TA/ • link from SVD2 home page also available

  15. Schedule On schedule so far

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