System-on-Chip Data Processing and Handling Electronics

1. System-on-Chip Data Processing and Handling Electronics Igor Kleyner Orbital Sciences Corp. Rich Katz NASA Goddard Space Flight Center Hans Tiggeler University of Surrey

2. Outline • Introduction • Automated and Customized Generation of moderate size IP Blocks • Adjustment of HDL coding style for various Synthesis tools • Automated Verification of generated IP • Higher Level Automated and Customized IP Generation • Conclusions

3. Objectives • Increase design reuse • Decrease development time/effort • Achieve high reliability • Optimization for power/area • IP generation in blocks with only application-required functionality • Compact and efficient spacecraft instrument controllers and processors

4. An example of SoC implementation for SC instrument controland data processing SoC Custom Computing Engine Custom Computing Engine Sensor Sensor System Interface Controller Peripherals

5. Example of SoC Building Blocks • ROM • RAM • FIFO • LIFO • Register File • UART • Timers* • Microprocessor • ALU • CORDIC Function • Array Multiplier • Correllator • FIR • Sequencer • Controller • Data Logger • Data Encoder/Decoder

6. IP Generation Flow User's Parameters Written in Delphi(Pascal) Generates VHDL Code Controls Synthesizer(s) Generates Test Vectors Controls Simulator(s) KOMPILER Verification INTEGRATED ENVIRONMENT VHDL Code Test Vectors Synthesizer(s) Simulator(s) Speed Area Simulation Output Netlist

7. Kompiler SoC Block VHDL Generation • “Templates” for each block are pre-coded • GUI “front end” provides selection of various options to satisfy application requirements and allow for resources/features trade-off • Synthesis tool is selected • For some blocks, more than one coding “style” may be available • “Template” is tailored to selected parameters • Test Vectors generated • VHDL simulation to verify results

8. Kompiler - VHDL Generation User Data Input VHDL Coded for Selected Synthesizer Parameters Selection Coding Style Selection

9. Kompiler SoC Block Compilation and Verification • Block is synthesized utilizing different available tools • If more than one coding style for the block is available, multiple VHDL entities are created and compiled • Optimal solution (area/speed) selected • Block design is verified by gate-level simulation

10. Kompiler - Synthesizer Interface • Synthesizer Selection • Synthesis Parameters Choice • Execution via Command Interface

11. Kompiler - Simulator Interface

12. Sample Problem: Optimal Logic Structuring for Synthesis • Logically identical equations can be represented in different forms. • “1’s” can be grouped for minimization • “0’s” can be grouped for minimization • Lists can be made • ‘Bit-case’ format • ‘Word-case’ format • ‘Constant’ format • Each affects the results of synthesized output • Data dependent • Technology dependent • Revision dependent

13. Coding Styles

14. Effects of Coding Styles and Synthesis Tools

15. Effects of Coding Styles and Synthesis Tools (2) * * The synthesizer, although released, did not have all of the optimization algorithms implemented for SX at the time of this study.

16. Effects of Coding Styles / Synthesis Tools (3)

17. Other SoC Blocks RAM (Single or Dual Port) LIFO

18. Other SoC Blocks UART Transmitter UART Receiver Common Logic Blocks (e.g., count down chains) Can Be Reused for Multiple Instances

19. Next Level of complexity - 29KPL154 • Based on Am29CPL154 Field Programmable Controller design • Single-chip Field Programmable Controller • Used for implementation of complex state machines and controllers • Not used in space applications for radiation and power consumption reasons Programmable Controller as SoC Building Block • Customized to fit exactly the particular application requirements • Fully integrated into Kompiler environment • Utilizes previously developed smaller IP Blocks

20. Am29CPL154 Features • 512x36-bit Program ROM • 8 test inputs, optionally registered • 16 user outputs • 28 instructions including conditional branching, looping, subroutine call, multiway branching • 17-deep, 9-bit wide stack

21. 29KPL154 Capabilities Test In Address Selection Logic Count Register GOTO Stack Condition Selector PC Instruction Decoder Program Memory Pipeline Register Data Out • Stack depth selectable from 0 to 17 • Program Memory internal, external or a combination • Contents of Program optimized by Kompiler as ROM block • Instruction Encoding Optimized by replacing unused fields with “don’t_cares” • Program contents analyzed by Kompiler, only used instructions and test conditions implemented • 16 additional test inputs and 16 extra user outputs can be used Optimization Effort Concentrated In Darker Shaded Blocks

22. 29KPL154 Customization Optimized ROM Contents VHDL Output Assembler Processing Stack Sized Appropriately Program Code File Customized Instruction Set Optional Extra User Outputs Optional Extra Test Inputs

23. KPL Blocks Customization Effects Act 3 Modules used (synthesized using ActMap)

24. Controller Customization Effects

25. KPP - Preprocessor for VHDL • Conditional Compilation • #ifdef, #ifndef, #else, #endif • supports nesting • supports logical operators • #ifdef Synplicity OR Exemplar • Include files • For Construct • supports nested loops • Extensive error checking • Other miscellaneous features

26. Conclusions • Moderate size customized blocks of IP can be used in SoC applications for SC instrument controls and custom data processing tasks • GUI-enabled integrated environment including HDL generation, synthesis and simulation allows faster and more reliable design of SoC components • Combining HLL-based software with HDL permits a flexible approach to hardware design. • Various synthesis tools perform identical tasks with various degree of efficiency depending on the style of coding. Results are sensitive to the specific data content. • Small processors can fit in the smaller, radiation-hardened FPGAs. • Optimizations have been identified in processor design for minimum area/power consumption, critical for compact, low power instrumentation.