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Coldfire Computer Final Presentation

Coldfire Computer Final Presentation. Josh Hudgins Randy Jedlicka Drew Larson. Project Staff:. Abstract.

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Coldfire Computer Final Presentation

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  1. Coldfire ComputerFinal Presentation Josh Hudgins Randy Jedlicka Drew Larson Project Staff:

  2. Abstract The central objective for this project is to produce a better lab for CPSC 462 students. With this in mind, several labs must be laid out as tasks for these students to perform. In summary, the main tasks that must be accomplished to produce the ColdFire microcomputer, for these labs, are the following: • Design Modification/Inspection of previous PROTEL layouts produced by Legendary Group 5 • Production of PCB by 3rd party manufacturer • Assemblage of components to completed PCB • Programming of Flash Memory with “monitor” program via JTAG connector • Porting of VxWorks OS to Flash Memory

  3. Objectives & Deliverables MAIN GOAL: Develop working computer using the Motorola Coldfire Processor • Evaluate the current status of the previously existing hardware designs • Redesign (if necessary) • Complete PCB layout with Protel • Send designs off to have manufacturer fabricate PCB

  4. Objectives & Deliverables (cont.) • Mount all components onto board • Port dBug monitor to Flash ROM • Port VxWorks to Flash ROM • Test Completed design with Dumb Terminal • Rewrite Labs for CPSC 462

  5. Evaluate/Redesign existing hardware designs in Protel • Component change • Flash: AM29F040 Vs NEC EEPROM • Schematic Corrections • Power line connected to ground? • New lines for new flash

  6. Full PCB Block Schematic

  7. PCB Layout • Completely redone • Board dimension • Layers of the board • Component placement • Trace routing

  8. CAD PCB Layout

  9. PCB fabrication • AP circuits required files: • Gerber Top and Bottom Layer, NC Drill, Drill Tool Size, and Aperture Table • Manufacturing delays • Short on board from 2 holes • Free drill bits

  10. Mounting components on PCB • 160-pin processor socket • The 96-pin Connector • The BDM Connector • Resistors and Capacitors • Power ports • The Under Voltage Sensor

  11. Completed PCB

  12. dBug Monitor Development Environment • Win32 and SunOS versions • Directory Structure • Use of Makefiles • Problematic Issues • Compiler Problems (EGCS1.1.1) • Makefile Issues • Board Specific Matters

  13. dBug Monitor Development Environment (cont) • Board Specific Monitor Program • Adapted MCF5206AN • Compiled Using Make Files

  14. Write dBug Monitor Program

  15. dBug Monitor ProgramPort into memory by use of JTAG

  16. Port dBug Monitor to Flash • JTAG Boundary Scan Technology • Specific Files Needed • Protel - Netlist • Motorola - BSDL • Converted to EDIF (Electronic Design Interchange Format) • Component File • Sel File - Directory Structure

  17. Port dBug Monitor to Flash • Installation Problems • WindowsNT / Windows2000 • Device Recognition • Incompatible Protel file • Error: No BST devices in design

  18. Port dBug Monitor to Flash(Results) • Placed DBUG monitor program in JBC3710 • Performed integrity checks of Monitor program • Successful • Continuing to resolve JTAG programming issues with Technical Support Personnel

  19. VxWorks Operating System • The BSP for the SBC5206 board sent to us by Wind River • Unattempted: The OS will be ported to the board via serial port and dBug monitor program

  20. Rewrite Labs for CPSC 462 • Adapted labs for use with our board • Updated addressing information • Updated components and pinouts • Deleted unusable labs • Did not get to attempt these labs

  21. Proposed Project Schedule

  22. Project Schedule Followed

  23. Conclusion • Completed Objectives: • Printed Circuit Board • Board Specific Monitor Program • Lab Manual • Partially Complete Objectives: • Port the Monitor to Flash • Uncompleted Objectives: • Port the Monitor to the Flash • Port VxWorks to the Flash

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