It’s The Core & Much More ….

1. It’s The Core & Much More …. Key Success Factors to 32-bit MCU Design Ying-wai Ho General Manager, MIPS-Shanghai MCU Technology and Application Forum

2. The Heritage of the MIPS Architecture • Pioneered by Stanford President John Hennessy in the 1980s • Pure and elegant RISC architecture • Clean, fast, efficient • Designed for performance • Now the architecture of choice for multimedia, home networking & beyond • Innovation continues by MIPS and licensees including Altera, Broadcom, Cavium, ICT, NEC, RMI Corp., Toshiba and others Widely used, widely taught architecture withmillions of lines of code written for it Photo: In 1984, Stanford computer scientists John Shott, John Hennessy and James D. Meindl brainstorm about the MIPS project (Photo: Chuck Painter)

3. MIPS-Shanghai - China Engineering Center Dedicated Shanghai-based MIPS design & engineering center—hardware & software Only leading processor company developing cores in China New M14K and M14Kc soft cores based on microMIPS ISA designed and developed entirely in China • Expanding Shanghai engineering team • Leveraging China talent and cost structure • Future plans for expanding operations in China to take on more engineering projects China Engineering Center

4. A Systematic Philosophy for Design Success microMIPS Advanced Code Compression 2010 Coherent multiprocessing 2008 Superscalar Performance 2007 Efficiency and Performance DSP Extensions Multi-threading 2006 2005 Microcontroller-specific cores 2002 Highest performance, synthesizable, licensable 32-bit cores 2001 MIPS32 and MIPS64 Architectures 1999 1991 Industry’s First 64-bit microprocessor Foundation for Success Built on MIPS’ Legacy of Scalability

5. Industry’s Most Scalable Processor Architecture 64-bit Networking And everything in between 32-bit Microcontrollers

6. Microcontrollers: Proliferating MIPS Architecture Performance and power efficiency leadership Over 20 MCU Licensees including: Microchip—number 1 MCU provider32-bit PIC32 MCUs based on M4K core Expanding family of core products M14K, M14Kc Addressing MCU design challenges real time operation, small size, low power Extending MIPS Architecture microMIPS ISA code size reduction Proliferating MIPS architecture to large community of developers

7. Key Success Factors to 32-bit MCU Design BEST ARCHITECTURE HIGH PERFORMANCE MCU FEATURES LOW POWER COMPLETE TOOLS LARGE ECOSYSTEM SMALL SIZE

8. MIPS Architecture

9. Wide Range of MIPS 32-Bit Processor Core Families 24KE M14Kc 24K M14K 2010 EEPW - BEST IP award MIPS32 M14K & M14Kc (1-4 cores) Max ~1.5GHz prod (40nm) >12,000 Coremark 10,000 DMIPS @ 1.25 GHz Coherent Multiprocessing 74K 34K 1004K 1074K 4KE Superscalar; 15-stage pipeline>1.5GHz prod, >2.4GHz typ (40nm)>6000 Coremark @ 2.4GHz Multi-Thread & Mult-Core Processing Single threaded performance Coherent Multiprocessing M4K 4KS Mid-Range 8-stage pipeline DSP extensions900MHz prod (65nm) Multi-threading Smaller & faster than Cortex M3 5-stage pipeline 1.48 DMIPS/MHz 300MHz (65nm LP) 2.6 CoreMark/MHz >30% smaller code size MCU, Embedded 5-stage pipeline 1.5 DMIPS/MHz Low area & power microMIPS advanced code compression & Enhanced MCU Features Broad range of synthesizable processors optimized for high performance & low power

10. Architecture for Performance – M4K/M14K Family • Classic RISC deep pipeline • Single cycle throughput • Single operation instructions • Simple 32-bit addressing modes and 32-bit data bus • Less speculative execution • Efficient branching. No need for branch prediction. • Compatible with 32- and 64- bit architectures. • Many architecture extensions : ASE, UDI, COP, SPRam… 1.5 DMIPS/MHz

11. Microchip PIC32 Performance +30% +20% EEMBC Coremark benchmark scores MIPS M4K 80MHz, 2 wait state, PIC32 outperforms other MCU devices operating at 120/100MHz, 0 wait state ARM Cortex-M3 ARM Cortex-M0

12. Architecture for Low Power • Elegant architecture • Deliver the performance needed with lower frequency and smaller area • Power reducing instructions • Software controlled power-down via WAIT instructions • Invokes SRAM sleep modes • High code density Instruction sets, microMIPS & MIPS16e • Reduce system level memory and overall bus traffic • Registers & handshaking signals for system power control • Fully static design • Allows on-the-fly changes • Fine-grain clock gating to reduce dynamic power • Automatically shuts down unused logic • Clock tree at root shuts down, wake up by external event • Voltage/Frequency scaling support • Compatible with major DVFS IP • Low power EDA flow support • Reference flow script support for all major EDA vendors physical design tool chains.

13. Power Consumption – M14K Power (mW) Speed Optimized Normal Mode Power (Dhrystone tight loop) Area Optimized 38.7 Speed Optimized Sleep Mode Power 30.7 Area Optimized 180G 130G 13.7 90G 8.1 65G 11.3 6.3 2.75 2.5 1.2 0.73 0.34 0.30 0.23 0.19 0.08 0.08 130 50 215 100 280 100 310 150 Target Freq (MHz)

14. Architecture for Minimum Code Size microMIPS ISA – Maintains MIPS32 assembly code structure • Complete Standalone ISA (Instruction Set Architecture) • Combines 16- and 32-bit instructions in a single ISA • Recoded MIPS32 & MIPS64 instructions • Includes 15 new 32-bit and 39 new 16-bit instructions • Frequent instructions and macros re-encoded to 16 bits • High Performance • Code Size : >30% code size reduction; • Functional : MIPS32 level performance; 1.48 DMIPS/MHz, 2.6 CoreMark/MHz • Compatibility • Supports MIPS32 and MIPS64® architectures • Supports co-existence with legacy MIPS32 decoder • Supports all MIPS ASEs • Configurability • microMIPS is build time configurable • Development Support • SW & HW tools – software toolchain, compiler, debug probe • 3rd party ecosystem – RTOS, OS, tools

15. microMIPS Code Size Benchmarks

16. Prologue ISRn Chaining ISRn+1 Epilogue MCU Application - Specific optional features • Reduced Interrupt Latency • Enhanced Interrupt Interface • Vectored Interrupt & External Interrupt Controller modes with high number of inputs • Multiple Shadow Register Sets • Multiple GPR’s for fast Interrupt service & context switching without save & restore • Atomic Bit Instructions • Bit-set & Bit-clear for Read-Modify-Write semaphore manipulation. • Flash Access Accelerator • Pre-fetch buffer scheme for slow memory access. • Parity Support for on-chip memory • Increase system reliability if needed. • Enhanced Debug Capabilities • Multiple program/data trace & profiling modes • Low overhead, low cost EJTAG • DFT Coverage • Compliant with ATPG Scan Test and Memory-BIST to achieve high test coverage IRQn IRQn+1 Cycles 10 4 7 21 cycles total

17. M14K Core Features Instruction Pre-fetch Enhanced iFlowtrace PC Sampling Fast Debug Channel 32 GPRs Shadow Regs microMIPS & MIPS32 Instruction Decoder Multiply Divide Unit Reduced latency Enhanced Vector/Priority AHB-Lite Parity CorExtend/UDI Co-Processor Low Power 5-stage Pipeline 1.48 DMIPS/MHz Atomic Bit Instructions Retained Features New/Enhanced Features

18. M14K vs Cortex-M • High Code Compression at MIPS32 performance • Same software platform • Maintains efficiency • Best Performance • Best Real-Time Performance • Fastest Interrupt Response • Reduced Dev. Time • Fast Time to Product • Fast Code Execution • Scalable • Uses std interfaces • Expandable • Customizable

19. Cores: MIPS vs. ARM • M14K can be configured to be equivalent to a Cortex-M3, M1 or M0. ‘3 cores-in-1’ • With more features, more options • Higher performance, more efficiency • Lower power, smaller area • Single development system • Experience in design > + +

20. Strategic Ecosystem for Success RTOS/OS Graphics Video Audio VoIP Foundries Networks Design Services Industry Orgs Wireless Stacks User Interfaces SoC IP Security EDA/ESL Development Tools Complementary IP and Enabling Technologies The right relationships to speed customers’ SoC development

21. MCU & Embedded Solutions Summary Ecosystem Development Support SG++ SysNav SEAD-3 Debug / Profiling EJTAG iFlowtrace Fast Debug Channel Application-Specific Features Reduced Latency microMIPS Flash acceleration AHB-Lite Cache controller TLB MMU Parity Efficient Base Architecture High Performance Small Size Low Power SRAM I/F MIPS32 Release 2 32 GPRs MDU CorExtend/UDI