Electronics, Trigger and DAQ/online for SuperB: summary of the SLAC workshop.

1. Electronics, Trigger and DAQ/online for SuperB: summary of the SLAC workshop. Dominique Breton D.Breton, SLAC SuperB Workshop – October 9th 2009 D.Breton, SLAC SuperB Workshop – October 9th 2009

2. Status of overall system architecture D.Breton, SLAC SuperB Workshop – October 9th 2009

3. A few words about ETD parallel sessions • Despite the absence of a lot of engineers (who attended remotely), we had two interesting sessions • first one was dedicated to general system elements • second one was dedicated to front-end electronics • We are really going ahead on most on the elements of the system architecture • Commercial solutions emerge for the Clock & Control links • A first proposal for the internal architecture of the FCTS system has been presented • Steffen introduced us to the online world. • We have to define the boundaries of this new item and define its connections with other subsystems • Progress was shown in the conceptual design of the front-end electronics for the subdetectors D.Breton, SLAC SuperB Workshop – October 9th 2009

4. COTS for timing distribution • DS92LV18 is an off-the-shelf SerDes with fixed latency and low jitter:-> promising candidate for timing distribution on detector • Error recovery has been characterized to evaluate the impact on the FCTS system design • Compatible with FPGA embedded SerDes, to design hybrid links(FPGA <-> DS92LV18) • 1 Gbit/s payload bandwidth, enough to sustain FCTS traffic (possibly FEE-to-ROM ?)

5. SerDes rad-tolerance and tests • SerDes manufactured on National CMOS8 process (0.25 um CMOS) • Slower CMOS8 serializers already qualified by ATLAS, CMS • According to the vendor, device should be tolerant to 100 kRad (TID) • No quantitative data on SEU/SEE • Rad test at LNS (Catania, Italy) in 2010 using 62 MeV proton beam • Positioning assisted by package radiography and chip layout (already available)

6. What is Online/DAQ? • Philosophical Question • Not “Offline”? • Where you have only one chance to do things? • Boundaries (Electronics, off-the shelf or commodity hardware / software) are getting fuzzy. • Glue that combines all the systems necessary to take data • Data path / vs. non data path • No answer here. Diagram of components of an Online system is on the right (biased by BaBar) • Many pieces to an Online system • Will need a few iterations on boundaries S. Luitz

7. FCTS architecture FCTM 1 Readout Supervisor 1 FCTM 2 FCTM 5 Throttle Switch FCTS Switch EMC FE IFR FE SVT FE DHC FE PID FE ReadOut Board ReadOut Board ReadOut Board ReadOut Board ReadOut Board Clock generator module Global Level 1 trigger (GLT) Local trigger L1 FCTS master : FCTM ECS Slow throttle Fan-in / Fan-out : supports partitionning Front-End electronics ReadOut Module Event building network

8. Proposal of FCTS boards Backplane Control & Distribution module Control Link Switch module FCTM module Throttle Switch module

9. Minimum FCTS crate (5 partitions) L1 ROM Throttle ECS CCL L1 trigger MachineClock CCL FE & ROM Throttle & IP L1 Fast Throttle Clock ECS CCL Control & distribution L1 CCL duplicator EMC CCL switch DHC CCL switch SVT CCL switch PID CCL switch IFR CCL switch FE EMC FCTM FE DHC FCTM FE IFR FCTM FE SVT FCTM throttle Switch FE IFR FCTM

10. FCTS: still to be defined • Granularity of detector partitioning: • Nbof FCTMs & Switch modules = number of partitions • 8 looks like a maximum to fit in the crate. Is this enough ? • If subdetectors need a high number of CCL links, duplicator boards can be mounted in auxiliary crates. • Links between FCTS and other modules in safe area have to be defined. • Protocol should be emulated by FPGA. • Should we have a common protocol for all links with free hardware ? • Or a common hardware (mezzanine) with open protocol depending on data rate ? • Standard crate (AdvancedTCA) or custom one ? • Common mezzanine for ECS & CCL links on front-end side ? • permits delivering the clock without a working FCTS • lower price & surface

11. Highlights on the subsystems: SVT (1) FE chip Layout (32x128) – preliminary • Front-end prototype chip for hybrid pixel “in production”. Test in 2010. • 130nm design • Prototype Al bus: should be available soon • ready to start testing the electrical characteristics of the bus Prototype

12. Highlights on the subsystems: SVT (2) • Mixed link solution( HDI to transition card): • some tests performed on LOC serializer => waiting for the LOC2 version • commercial devices need to be tested • Link test setup in progress • FPGA part is progressing well even if with some delays • Other parts: moves slowly, awaiting some crucial part to take decisions on PCB design

13. Highlights on the subsystems: DCH (1) Proto I DC Instrumentation Instrumentation for DC proto 1: 24 channels Preamplification/Amplification/Discrimination VTX main features Amplifier/Discriminators Pre I/O Analog Outputs Pre LVPS (remote sensing) Test Inputs VTH set Digital outputs 13

14. Highlights on the subsystems: DCH (2) Cluster Counting – Test Bench Cluster counting: local derivative method Buffer 5 ns/div 10 mV/div AD96687 Gain - VOUT-PRE + Delay 5 ns/div 10 mV/div Buffer+VTH AD8002 ≈ 6 ns System Dead Time 5 ns/div 10 mV/div Delay = 3 ns Delay = 5 ns 14

15. Highlights on the subsystems: PID (1) • Electronics for the barrel : • The test with the BLAB2 (2.5Gs/s) chip are ongoing on the telescope at SLAC. We measure a Cherenkov angle resolution as expected. But firmware needs some fixes to perform a timing resolution at the level of 100-200ps. These fixes will be installed in the CRT in December. At that point we will start taking data with capability of correcting the chromatic corrections. • BLAB3 version is expected and will be tested next month. Its sampling rate jumps from 2.5 to 4 Gs/s. • We already have a 16-channel • 100ps TDC in hand. We will redesign • the readout part of the chip to match • a MHz count rate per channel. • We decided to measure both time • and charge information for each • channel both for time walk corrections • and physics purpose. • We plan to incorporate this new TDC electronics in the CRT readout as soon as possible, and also to restart the scanning setup. D.Breton, SLAC SuperB Workshop – October 9th 2009

16. Highlights on the subsystems: PID (2) • Electronics for the forward PID: • We need at least a 10 ps resolution for the electronics. Analog memories are the only candidates therefore. • The test of Gary Varner’s TARGET chip gives very encouraging results: with ~ 40 pe per laser pulse (equivalent to particles within a 1cm-long quartz radiator), the resolution is 13 ps. • - > 2.5 GSa/s waveform digitizing electronics with 250 MHz of BW can compete with Ortec electronics. The results were surprisingly good. This is actually due to a saturation of the signal slope in the input amplifier => discovery of a new measurement method ? • The Wave Catcher board (from LAL), also based on fast analog memories(3.2 GS/s), which recently proved a resolution below 10ps, has been given to Jerry and tested on his bench Wednesday. D.Breton, SLAC SuperB Workshop – October 9th 2009

17. Highlights on the subsystems: EMC (1) • Proposal for a new design of the ADB board compatible with the old mechanical structure • Use two gains (x1 & x32) and a new ADC with more bits (12bits instead of 10bits) • Source calibration mode setup is foreseen. D.Breton, SLAC SuperB Workshop – October 9th 2009

18. Highlights on the subsystems: EMC (2) • Design of a new VFE board for EMC FWD with x1 and x32 outputs compatible with Barrel preamp (light detector will be either APD or PIN diode). • All boards should be ready for testing in April 2010. • Tests with APDs and PIN diodes in beam are foreseen. • Trigger primitives have not to be forgotten. D.Breton, SLAC SuperB Workshop – October 9th 2009

19. Highlights on the subsystems: IFR (1) • Timing readout for Barrel, binary readout for endcaps. CAEN TDC used in the DAQ for prototype readout TDC board to be developed for the actual DAQ for the IFR Outline of the “IFR_ABCD” card (Amplifier, Bias, Comparator,DataProcessing) • SuperB IFR prototype: • 5 layers of x-y scintillators, 1 cm thick, read in binary mode • 3 layers of scintillators 2 cm thick, read in timing mode D.Breton, SLAC SuperB Workshop – October 9th 2009

20. Highlights on the subsystems: IFR 2) • Prototypes test boards for the two options (timing and binary readout) have been shown. Both are based on Cyclone III development kits. • Problems remain with finding a multi-channel TDC working @ 56MHz … and also to deal with the trigger time window with available circuits. • Study of data rates push to a reduction of the trigger window well below 1µs. D.Breton, SLAC SuperB Workshop – October 9th 2009

21. Conclusion • Despite the holidays, we went on moving forward during the last months. • Technical solutions emerge for most elements of the architecture. • Since Perugia, a new chipset has been tested for Clock and Control links and an internal architecture has been proposed for FCTS. • We need to get from each FE subsystem estimations not only of the number of readout links but also of CCL and ECS links. • This indeed has a influence on FCTS architecture, especially at the level of the duplication needs. • But L1 trigger still remains uncovered ... • We started discussing about online/DAQ. • We have to define the boundaries of this new item and define its connections with other subsystems • A working meeting will take place at CERN beginning of November, including discussions about the Level 1 Trigger • We are still waiting for a map of the estimated radiation level on the detector • We have to define the fields and to share the work for the ETD white paper writing D.Breton, SLAC SuperB Workshop – October 9th 2009