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Lecture 2.0

Lecture 2.0. Thermodynamics in Chip Processing Terry Ring. Field Effect Transistor (FET). Gate Oxide. Capacitor connecting Gate to center of npn or pnp heterojunction Capacitance Area Thickness Dielectric constant of oxide Dictates the Speed of the Switch. Gate Oxide Capacitance.

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Lecture 2.0

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  1. Lecture 2.0 Thermodynamics in Chip Processing Terry Ring

  2. Field Effect Transistor (FET)

  3. Gate Oxide • Capacitor connecting Gate to center of npn or pnp heterojunction • Capacitance • Area • Thickness • Dielectric constant of oxide • Dictates the Speed of the Switch

  4. Gate Oxide Capacitance C=oA/d =C/Co =1+e e = electric susceptibility

  5. Field Effect Transistor (FET)

  6. Silicon Oxidation • Thermodynamics • (yes/no? How Far? Heat/cool) • Furnace at T=850C • Pure Oxygen • Si + O2 SiO2 • Kinetics (how fast) • BL-Mass Transfer • J=Kg(CA-0) • SS-Diffusion • J=DO-SiO2 (dC/dx) • Heat Transfer • BL, q=h(T1-T) • Solid, q=kSiO2(dT/dx) • J=q/Hrxn

  7. Thermodynamics of Reactions • Thermodynamics Can Tell you Three Things • Is reaction spontaneous • Gibbs Free Energy, ΔGrxn(T) • Grxn<0, Spontaneous • Grxn>0, Non-Spontaneous • What are Equilibrium Ratios? • ΔGrxn(T)= - RT ln(Keq) • Does Reaction create heat? • Heat of Reaction, ΔHrxn(T) • Exothermic, ΔHrxn(T)<0, get hot! • Endothermic, ΔHrxn(T)>0

  8. Reaction to Make SiO2 • Si (s) + O2 (g)  SiO2(s) • Done in Vacuum Furnace. • Does the Reaction Go? • Po2 =0.001 atm • T= 600 C

  9. Gibbs Free Energy • Si (s) + O2 (g)  SiO2(s) • ΔGrxn(T)=GSiO2 (T)- GSi(T) - GO2 (T) = - RT ln(Keq) • -ΔGorxn(T)=GSiO2 (T)- GSi(T) - GO2 (T) • Keq=Xo2=Po2/PTot • If ΔGrxn(T)=0, then • ΔGorxn(T) = - RT ln(Po2) • GSiO2 (T)= ΔHSiO2(T) -TΔSoSiO2 • ΔHSiO2(T) =Hof-SiO2+To∫TCp-SiO2(T) dT • GSi(T)= ΔHSi(T) -TΔSoSi • ΔHSi(T) =Hof-Si+To∫TCp-Si(T) dT Grxn<0, Spontaneous webbook.nist.gov/chemistry/

  10. Po2 = 0.001 atm • T = 600 C ΔGrxn(T)= ΔGorxn(T)- RTln(Po2) -180 kcal/mole-(-10kcal/mole) = -170 kcal/mole Spontaneous!

  11. Want to Create O2 with wet H2 • H2O(g)   H2(g) + ½ O2(g) • Equilibium • ΔGrxn(T)= - RT ln(Keq) • Keq = (XH2 √Xo2)/XH2O • ΔGrxn(T)= ΔGH2 (T)+1/2 ΔGo2(T)- ΔGH2O(T)

  12. At • T = 600 C • What H2/H2O Ratio?

  13. Want to Create O2 with CO/CO2 ratio • 2CO2(g)   2CO(g) + O2(g) • Equilibium • ΔGrxn(T)= - RT ln(Keq) • Keq = (XCO2 Xo2)/XCO22 • ΔGrxn(T)= 2ΔGCO (T)+ΔGo2(T) - 2ΔGCO2(T)

  14. At • T = 600 C • What CO/CO2 Ratio?

  15. What Memory Chip Really Looks Like W

  16. Metalization • Transistor Contacts • Base • Emitter • Gate • Metal Deposition • Chemical Vapor Deposition

  17. CVD of Poly Si – Gate conductor • SiH4Si (s) + 2 H2 • 620C, vacuum • N2 Carrier gas with SiH4 and dopant precursor • Stack of wafer into furnace • Higher temperature at exit to compensate for gas conversion losses • Add gases • Stop after layer is thick enough

  18. CVD Reactor • Wafers in Carriage (Quartz) • Gasses enter • Pumped out via vacuum system • Plug Flow Reactor Vacuum

  19. CVD of W – Metal plugs • 3H2+WF6 W (s) + 6HF • T>800C, vacuum • He carrier gas with WF6 • Side Reactions at lower temperatures • Oxide etching reactions • 2H2+2WF6+3SiO2 3SiF4 + 2WO2 + 2H2O • SiO2 + 4HF  2H2O +SiF4 • Stack of wafer into furnace • Add gases • Stop after layer is thick enough

  20. Chemical Equilibrium

  21. DRAM Memory Cell W Si Column Line SiO2 Capacitor Gate or Row Line 1 Bit Wafer N P N

  22. CVD of SiO2 – Dielectric • Si(0C2H5)4 +7O2SiO2(s)+ 10 H2+ 8CO2 • 400C, vacuum • He carrier gas with vaporized(or atomized) Si(0C2H5)4and O2 and B(CH3)3 and/or P(CH3)3 dopants for BSG and BPSG • Stack of wafer into furnace • Higher temperature at exit to compensate for gas conversion losses • Add gases • Stop after layer is thick enough

  23. CVD of Si3N4 - Implantation mask • 3 SiH2Cl2 + 4 NH3Si3N4(s)+ 6 HCl + 6 H2 • 780C, vacuum • Carrier gas with NH3 / SiH2Cl2 >>1 • Stack of wafer into furnace • Higher temperature at exit to compensate for gas conversion losses • Add gases • Stop after layer is thick enough

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