Lecture 4 9/9/11

1. Lecture 4 9/9/11 Common Courtesy – Leave communal books in the lab web site www.ee.duke.edu/~jab/ece154 Homework • For Wednesday 9/14, read Ch3, p. 76-120 • For Friday 9/16, Read Ch3, p. 120-135 • For Wednesday 9/14, Lab 1 Simulation • For Friday 9/16, Lab 1 Hardware

2. Multiplication • recall 8-bit times 8-bit yields potentially 16-bit result • D register on 6811 is the union of the A and B registers (each 8 bits) • on 6811, only hardware multiply is unsigned 8-bit times unsigned 8-bit into D register: divide and conquer for 16x16 • 6812 augments with 16x16 signed and unsigned

3. Division • Inverse of 8x8=16 problem; need to divide 16 bit thing by 8 bit thing to get 8 bit answer • What if you divide 8 bit by 8 bit? • 6811: 2 native division instructions, both 16 bit divided by 16 bit; fdiv pads dividend out to 32 bits first with 0’s though, idiv does not

4. Architecture review from embedded systems perspective • Emphasis on I/O, not data path or control flow (backwards from ECE152) • Recall a microcomputer (like the 68HC711E9) is a microprocessor (the 6811 in this case) plus (typically on the same chip) enough memory, bus, and I/O capability to be useful as a complete computer system as is.

5. Memory-Mapped I/O – recall memory maps • MC68HC711E9 (single chip mode) $0000-$01FF RAM - 512 bytes RAM $1000-$103F I/O - i.e. 64 byte-wide I/O addresses $B600-$B7FF EEPROM - 512 bytes EEPROM $D000-$FFFF ROM (12K, possibly UV erasable but viewed as permanent). • MC68HC812A4 $0000-$01FF I/O - i.e. 512 byte-wide I/O addresses $0800-$0BFF - RAM $F000-$FFFF - ROM (UV)

6. Even lower end • MC68HC705J1A • 20 pin package • 1240 bytes ROM • 64 (!) bytes RAM • 14 I/O pins (2010: $4.34/$3.18) • MC68HC705KJ1 (phased out) • 16 pin package • 10 I/O pins • $2.66 in qty 1 from DigiKey 9/05; $1.22 qty 1000 (2009:NA) • compare to $16.70 qty 1 for MC68HC711E9; $10.70 qty 1000 (2010: $20.34/$15.97 Newark)

7. Major components of an architecture (embedded view) • Bus Interface Unit (BIU) – handles timing details of reads and writes; EAR is one component • Control Unit (CU) – handles sequencing of operations; IR is one component • Registers – for high speed storage (relatively speaking!), typically at least PC, SP, CCR, an index register or two, and one or more accumulators for data • typically in embedded system PC will point to ROM (or EPROM), SP to RAM • Cache? • Finally: ALU – relegated to “The ALU performs arithmetic and logic operations.”

8. (Generic) Instruction cycle • Instruction Fetch • here, 1 byte at a time; some instructions are multibyte; Decode and EAR calculation are lumped into Fetch • Data Read (when required) – retrieve data from EAR • Operation (i.e. execute) – use ALU, set CCR • Data Store (when required) – write result to EAR As Valvano notes, only Fetch is mandatory in this view, though some operation is usually performed; others are instruction dependent.

9. Common Architecture of 6811/12 • 6812 is almost (not exactly!) a superset of 6811 • Most 6811 programs will work on a 6812 with minor modifications (esp. w.r.t SP) • Register architecture: 7 common regs, 8 common names CC: 8-bit condition code reg with SXHINZVC flags D: 16-bit accumulator; D=A:B for 8-bit regs A and B; A is MSByte in 16-bit ops X,Y: 16-bit index registers for address calcs (pointers) SP: 16-bit stack pointer PC: 16-bit program counter

10. Stack Discipline – ugh – and other inconsistencies • 6811: SP+1 points to top element of stack (i.e. first free entry at SP) • 6812: SP points to top element of stack (i.e. last occupied entry) While we are griping, Valvano points out “Motorola should have developed versions of the 6812 with I/O ports and pinouts identical to its most popular versions of the 6811.” And how can we forget – opcodes are different, so reassembly is always required!

11. Condition codes • As we have already noted, nearly every operation sets appropriate condition codes; it is programmer’s duty to check them when necessary. • C,V,Z,N,H: numeric flags set by ALU • C: Carry/Borrow, or unsigned overflow • V: Signed (2’s complement) overflow • Z: Zero (last result was exactly 0) • N: Negative (last result was negative)

12. Condition codes, cont. • H: half-carry from bit 3, i.e. nibble carry (useful for BCD) • I,X,S: Control flags set by programmer • I: 1-bit IRQ mask register (mask further interrupts on the single IRQ line) • X: XIRQ interrupt mask (X=0 allows XIRQ interrupts – once set to 0 cannot be changed by software – single high priority interrupt) • S: Stop disable: when S=1, the STOP instruction is DISABLED!

13. Nomenclature for describing 6811/12 instructions w: 8-bit number, can be signed or unsigned n: signed 8-bit number (-128 to +127) u: unsigned 8-bit number (0 to 255) W: 16-bit number, can be signed or unsigned N: signed 16-bit number (-32768 to 32767) U: unsigned 16-bit number (0 to 65535) =[addr]: 8-bit read from addr ={addr}: 16-bit read from addr big endian =<addr>: 32-bit read from addr big endian [addr]: 8 bit write to addr {addr}: 16 bit write to addr big endian <addr>: 32 bit write to addr big endian

14. So, for instance: ADDA: 8-bit add into register A • immediate: ADDA w ;AA+w • extended: ADDA U ;A A+[U] While we’re at it, format of a 6811/12 assembly language instruction label opcode operand comment MAIN adda #10 RegA=RegA+10 Only opcode mandatory, but in this class comment might as well be!