Encryption / Decryption on FPGA Final Presentation

1. Encryption / Decryption on FPGA Final Presentation Written by: Daniel Farcovich ID. 303710388 Saar Vigodskey ID. 039608153 Advisor: MonyOrbach Summer Semester 2011 (August – December)

2. Project Goal • Creation of data cryptography system using hardware components of type FPGA DE2-110 with cyclone II EP2C35 device, designated to external memory devices such as Disk-On-Key • The system will encrypt the data efficiently according to standard encryption algorithms, which are being used by the private sector. • The encryption will be symmetric or asymmetric and made by keys.

3. Algorithm Description • Most of the AES calculations are made through 10 rounds. Each round consists 4 steps, state transformation. The state describes the current data block as a 2D, 4X4 array of bytes. In each round a “Round Key” is created by the key-expansion process. • AES encryption includes 4 steps: • SubBytes • ShiftRows • MixColumns • AddRoundKey

4. x9 • Cipher • data AddRoundKey SubBytes ShiftRows MixColumns AddRoundKey • encrypted • data SubBytes ShiftRows AddRoundKey Key Expansion • key Inv ShiftRows Inv SubBytes AddRoundKey • data • encrypted • data AddRoundKey Inv ShiftRows Inv SubBytes AddRoundKey Inv MixColumns • Inverse Cipher • x9

5. Full Piped ArchitectureTop Level INPUT data [0..127] – raw data ed – ‘0’ for encryption, ‘1’ for decryption clk – system clock rst – high active key[0..127] – 128 bit cryptography key OUTPUT data_out [0..127] – processed data valid_out – ‘1’ when key expansion is ready

6. Round Module Cryptography direction determined using ‘e_d’ signal. When encryption (decryption) is needed, the decryption (encryption) components are not active.

7. AES Compilation Summery

8. Post Synthesis Simulation Expanded key is ready Data input Set key. Reset Key expansion process (40 cycles) System is ready to receive data, set data. Each cycle set 128 input data. First output is given after 10 cycles from step 4.

9. Post Synthesis Simulation

10. Timing Analysis According to Quartus the clock frequency is 57.8MHz. After some testings, the system operates as needed at 50MHz. Throughput: processing 6.4 * 10^9 bit/sec or 763 Mbytes/Sec For comparison, software implementation of AES algorithm on Pentium M 1.7GHz reaches 60Mbytes/sec. Latency: each block goes through 10 rounds in AES. Each round lasts 20nsec. Therefor the latency is 0.2µsec.

11. Testing and verification start Vhdl editor synthesis program no Modelsim simulation Post synthesis simulation Testing using Signaltap and memory sampling ok ok ok yes yes yes no no end • The verification was done using Example Vectors taken from the AES standardand typical inputs. • The final test is to encrypt data using the encryption block and to decrypt the output using the decryption block and compare the result with the original data.

12. Testing Environment DE2 FPGA SRAM

13. Verification System

14. Verification Waveform 2 rounds as previously described. A: FIFO_IN is filled with data from SRAM. B: Expanded key is calculated, encryption/decryption is being performed. Calculated data is written to FIFO_OUT. C: Data is written from FIFO_OUT to SRAM.

15. Verification Process • Writing test pattern to SRAM using DE2 Control Panel Program. • Running Encryption and Decryption. • Comparing original data and decrypted data. • Tests were performed with different keys. • Patterns used in tests: • Random text from the web. • Random values. • Incremental Values (0123456789ABCDEF) • Decremental Values (FEDCBA9876543210) • Constant Values (7777…) • Test Vectors from standard (3243F6A8885A308D313198A2E0370734).

16. Bugs • Dual Port ROM – bug was found in Modelsim Gate Level simulation. Second data output changes one cycle later than expected. • No problems were found during verification. The bug is only at Gate Level simulation.

17. Bugs 2. Inverted FIFO Values – FIFO components show inverted words in output blocks. for example: The solution was correction component attached to the FIFO, which reorganized the words inside the block.

18. Conclusions • All project goals were reached. • Before implementation, an architecture has to be designed, and compared to different possible implementations. • Always check if the best architecture fits the FPGA area. • During coding, use the coding guidelines according to the FPGA manufacturer. • Code robustness – keep the code simple. Code changes with little affect on other code parts. • Plan the project timetable, and allow enough time for testing and debug (at least as long as the design took).