Tuning of Loop Cache Architectures to Programs in Embedded System Design

1. Tuning of Loop Cache Architectures to Programs in Embedded System Design Susan Cotterell and Frank Vahid* Department of Computer Science and Engineering University of California, Riverside *Also with the Center for Embedded Computer Systems at UC Irvine This work was supported in part by the U.S. National Science Foundation and a U.S. Department of Education GAANN Fellowship

2. Traditional Core Based microprocessor architecture Opportunity to tune the microprocessorarchitecture to the program Introduction

3. I-cache • Size • Associativity • Replacement policy Mem Processor I$ I$ I$ D$ • JPEG • Compression Bridge • Buses • Width • Bus invert/gray code JPEG JPEG JPEG USB CCDP P4 Introduction

4. Introduction • Memory access can consume 50% of an embedded microprocessor’s system power • Caches tend to be power hungry • M*CORE: unified cache consumes half of total power (Lee/Moyer/Arends 99) • ARM920T: caches consume half of total power (Segars 01)

5. Introduction Advantageous to focus on the instruction fetching subsystem Mem Processor I$ D$ Bridge JPEG USB CCDP P4

6. Introduction • Techniques to reduce instruction fetch power • Program compression • Compress only a subset of frequently used instructions (Benini 1999) • Compress procedures in a small cache (Kirvoski 1997) • Lookup table based (Lekatsas 2000) • Bus encoding • Increment (Benini 1997) • Bus-invert (Stan 1995) • Binary/gray code (Mehta 1996)

7. Introduction • Techniques to reduce instruction fetch power (cont.) • Efficient cache design • Small buffers: victim, non-temporal, speculative, and penalty to reduce miss rate (Bahar 1998) • Memory array partitioning and variation in cache sizes (Ko 1995) • Tiny caches • Filter cache (Kin/Gupta/Magione-Smith 1997) • Dynamically loaded tagless loop cache (Lee/Moyer/Arends 1999) • Preloaded tagless loop cache (Gordon-Ross/Cotterell/Vahid 2002)

8. L1 memory Filter cache (L0) Processor Cache Architectures – Filter Cache • Small L0 direct mapped cache • Utilizes standard tag comparison and miss logic • Has low dynamic power • Short internal bitlines • Close to the microprocessor • Performance penalty of 21% due to high miss rate (Kin 1997)

9. L1 memory L1 memory L1 memory Dynamic loop cache Dynamic loop cache Mux Dynamic loop cache Processor Iteration 1 : detect sbb instruction Iteration 2 : fill loop cache Iteration 3 : fetch from loop cache Cache Architectures – Dynamically Loaded Loop Cache • Small tagless loop cache • Alternative location to fetch instructions • Dynamically fills the loop cache • Triggered by short backwards branch (sbb) instruction • Flexible variation • Allows loops larger than the loop cache to be partially stored ... add r1,2 ... sbb -5

10. L1 memory L1 memory L1 memory L1 memory Dynamic loop cache Dynamic loop cache Dynamic loop cache Mux Processor Iteration 1 : detect sbb instruction Iteration 2 : fill loop cache, terminate at cof Iteration 3 : fill loop cache, terminate at cof Cache Architectures – Dynamically Loaded Loop Cache (cont.) • Limitations • Does not support loops with control of flow changes (cofs) • cofs terminate loop cache filling and fetching • cofs include commonly found if-then-else statements ... add r1,2 bne r1, r2, 3 ... sbb -5

11. L1 memory L1 memory L1 memory Preloaded loop cache Preloaded loop cache Mux Processor Iteration 1 : detect sbb instruction Iteration 2 : check to see if loop preloaded, if so fetch from cache Cache Architectures – Preloaded Loop Cache • Small tagless loop cache • Alternative location to fetch instructions • Loop cache filled at compile time and remains fixed • Supports loops with cof • Fetch triggered by short backwards branch • Start address variation • Fetch begins on first loop iteration ... add r1,2 bne r1, r2, 3 ... sbb -5

12. L1 memory ? Mux Processor Traditional Design • Traditional Pre-fabricated IC • Typically optimized for best average case • Intended to run well across a variety of programs • Benchmark suite is used to determine which configuration • On average, what is the best tiny cache configuration?

13. Evaluation Framework – Candidate Cache Configurations

14. Evaluation Framework – Motorola's Powerstone Benchmarks

15. Program instruction trace Loop selector (preloaded) lcsim Loop cache stats lc power calculator Loop cache power Technology info Simplified Tool Chain

16. original flexible preloaded (sa) preloaded (sbb) filter 30 105 • Configuration 30 • Preloaded Loop cache (sa), 512 entries, 3 loop address registers • 73% Instruction fetch energy savings • Configuration 105 • Filter cache, 1024 entries , line size 32 bytes • 73% Instruction fetch energy savings Best on Average

17. microprocessor architecture Core Based Design • Core Based Design • Know application • Opportunity to tune the architecture • Is it worth tuning the architecture to the application or is the average case good enough?

18. Best on Average • Both configurations perform well for some benchmarks such as engine and summin • However, both configurations perform below average for binary, v42, and others

19. original flexible preloaded (sa) preloaded (sbb) filter 31 30 105 Results - binary • Config 30 yields 61% savings • Config 105 yields 65% savings • Config 31 (preloaded/1024entry/2LAR) yields 79% savings

20. original flexible preloaded (sa) preloaded (sbb) filter 30 67 105 Results – v42 • Config 30 yields 58% savings • Config 105 yields 23% savings • Config 67 (preloaded/512entry/6LAR) yields 68%

21. v42 Best case : 68% (preloaded) Config 105: 23% Improvement : 45% adpcm Best case : 68% (preloaded) Config 105: 25% Improvement : 43% Average case Best case : 84% Config 30 : 73% Config 105: 73% Improvement : 11% jpeg Best case : 92% (filter) Config 30: 69% Improvement : 23% blit Best case : 96% (flexible) Config 30: 87% Improvement : 9% Results - averages

22. Conclusion and Future Work • Shown benefits of tuning the tiny cache to a particular program • On average yields an additional 11% • Up to an additional 40% for some programs • Environment automated but requires several hours to find best configuration • Current methodology is too slow • Faster method based on equations described in upcoming ICCAD 2002