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Computer Architecture

Computer Architecture. Lecture 5 Design Decisions for a 64-bit RISC Architecture Source of almost all Slide: Text Book. Addressing Modes. Addressing Modes. 1%. Memory indirect. 6%. 1%. 0%. Tex Spice gcc. Scaled. 16%. 6%. 24%. Tex Spice gcc. Register Indirect. 3%. 11%. 43%.

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Computer Architecture

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  1. Computer Architecture Lecture 5 Design Decisions for a 64-bit RISC Architecture Source of almost all Slide: Text Book

  2. Addressing Modes

  3. Addressing Modes

  4. 1% Memory indirect 6% 1% 0% Tex Spice gcc Scaled 16% 6% 24% Tex Spice gcc Register Indirect 3% 11% 43% Immediate Tex Spice gcc 17% 39% 32% Tex Spice gcc Displacement 55% 40% 10% 20% 30% 40% 50% Frequency of the addressing mode Summary of Memory Addressing Mode Summery of use of memory addressing mode 75% to 90 %

  5. Size of Displacement 45% 40% Percentage of Displacement 35% 30% 16-bit Displacement field will capture 75% to 99% 25% 20% 15% 10% 5% 0% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Number of Bits needed for Displacement

  6. Use of Immediate Operand

  7. Immediate Addressing Mode-Displacement distribution 45% 40% 35% Percentage of Immediate 16-bit Displacement field will capture 50% to 80% 30% 25% 20% 15% 10% 5% 0% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Number of Bits needed for Immediate Operand

  8. Distribution by benchmark size Double Word (64 bits) 70% 59% Word (32 bits) 29% 26% Floating point average Integer average Half word (16bits) 0% 5% Byte (8bits) 1% 10% 10% 20% 30% 40% 50% 60% 70% 80% Distribution of Data Accesses by Size for Benchmark Program

  9. Instruction Types

  10. Instruction Type Frequency TOTAL = 96%

  11. Instructions for Control Flow • The Measurements of branch and jump behavior are fairly independent of other measurements and applications. • Four types of control flow change: • Conditional branches • Jumps • Procedure calls • Procedure returns

  12. Floating point average Integer average 8% Call/return 19% Jump 10% 6% Conditional Branch 82% 75% 25% 50% 75% 100% Control Flow instructions into three classes Three classes of control flow instructions

  13. Not Equal 5% 2% 16% Equal Floating point average Integer average 18% Greater than or equal 0% 11% 0% Greater than 0% 44% Less than or equal 33% 34% Less than 35% 10% 20% 30% 40% 50% Frequency of Comparison Types in Branches Types of compares in conditional branching

  14. Branch distances in terms of number of instructions

  15. Conditional branch options • Conditional Code (CC) register • E.g. 80x86,ARM etc. • Tests special bit set by ALU operations • Advantage • Sometimes condition is set free • Disadvantage • CC is extra state. Condition codes constrain the ordering of instructions since they pass information from one instruction to a branch

  16. Conditional branch options • Conditional Register • E.g. Alpha, MIPS • Tests arbitrary register with the result of a comparison • Advantage • Simple • Disadvantage • Uses up register

  17. Conditional branch options • Compare and branch • E.g. PA-RISC, VAX • Compare is part of the branch. Often compare is limited to subset • Advantage • One instruction rather than two for a branch • Disadvantage • May be too much work per instruction for pipelined execution

  18. Summary of Analysis

  19. Encoding an instruction set

  20. Basic Blocks of a ProcessorMemory Model Basic Memory Operations Read/Load : Regs[Rx]  Mem[Address] Write/Store: Mem[Address]  Regs[Rx] Effective Address: Imm: Address =Imm Displacement: Address = Imm + Regs[Ra] Indirect: Address = Regs[Ra] Memory Address N-bit Data Out M-bits Data In M-Bits Read/Write

  21. Datapath or ALU Model Some Conditions Basic ALU Operations 1. AluOut = A op B 2. AluOut = A op Imm 3. Aluout = Shifted A by Shamt (Shift Amount), B is Ignored A, B and AluOut are same size (32 or 64-bit) What is the size of shamt? What is the size of AluOp? A Operand AluOut ALU B Operand Or IMM Shamt AluOp

  22. Register File Register File A Field ?-bit A data Out M-bits Basic Register File Operations 1. A = Regs[A field] 2. B = Regs[B field] 3. Regs[Write field] = Write Data if Register Write =1 B Field ?-bit B Data Out M-bits Write Field ?-bit Register Write Write Data

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