ECE 4110–5110 Digital System Design
ECE 4110–5110 Digital System Design. Lecture #27 Agenda Counters Announcements Finish reading Wakerly sections 8.1, 8.2, 8.4, 8.5 (Sequential timing, registers, counters, shift registers). Skip the AHDL and Verilog sections 8.2.6, 8.2.8, 8.4.5, 8.4.7, 8.5.7, 8.5.9. Counters.
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