EPA

1. EPA Jon Persinger Jonathan Snyder Devon Dallmann Henry Au-Yeung Khushboo Verma

2. Hardware System diagram 12V Power Regulation 5V, 10Apeak 3.3V 3.3V 1.8V 5V Hardware Debug 4x4 Test Pin ready interrupt TMS470R1A256 Driver Circuit 17 control lines CPLD 16x16 Solenoid Array 256k Flash Send data via SPI State Machine Compact Flash 12k RAM Get pic button

3. Compact Flash • Non-proprietary • Has built-in controller • Operation in PC Card Memory Mode; FAT16 format • Operates in 16-bit mode

4. Processor • Operates 24 MHz • 256K on-chip Flash (image processing requires lots of space) • 12k on-chip RAM • Use of Rowley CrossWorks and CrossConnect for programming and compiler • Olimex Dev Board • Open source code available for ARM7 architecture • Use of two High End Timers (HET) for PWMs • Built in SPI controller • Provides enough IO for Compact Flash communication in 16-bit mode

6. Controls Schematic

7. Driver • Verification of Driver circuit shown during PDR was completed successfully. • The addition of a dead time circuit was necessary in order to prevent the reverse current circuit from shorting the supply rails. • The layout of this circuit is shown here. Reverse Current CKT CLMN Select CKT CPLD Solenoid

8. Drive Schematic

9. PCB Layout • The PCB is a 4-layer 6.5” x 6.5” board with 2oz copper on signal layers and 1oz on internal layers. • Logic and current carrying grounds are isolated via a split ground plane. • Power planes are split to limit the current loops to the drive circuit per row. • A temporary hardware debug section including manual switches to control a 4x4 binary grid without the processor and CPLD. • High current traces were routed with copper pours and planes to allow for low voltage drops.

13. FPGA vs CPLD • CONS • CPLDs do not have to be reprogrammed at every power up (they are static memory not dynamic, a FPGA is programmed and loses its memory when the power goes off). So we'd have to add some sort of PROM (which Xilinx does sell and it's pretty cheap) to program a FPGA at every power on • FPGAs are only 2.5 and 3.3 volt compatible, not 5 volt, so we'd have to use step up and step down converters. CPLD is 5 volt compatible • 9500 series CPLDs hold their data for at least 20 years, and reprogramable 10,000 times • PROS • CPLDs cost more than FPGAs (cheapest Spartan III is $10 and has more gates in it than the 95288, which is $50) and have less gate space • CPLDs have ALOT worse timings than FPGAs, their setup and hold times are a lot longer, the gate delay is longer, the pin to pin delay is longer (all by about a magnitude of at least 10) • FPGAs typically come in smaller packages than CPLDs • In a CPLD programming is restricted to function blocks and macro cells, in an FPGA it is not (layout is more efficient in an FPGA)

14. FPGA Simulation/Timing Diagram

15. Solenoids • 1000 turns allows for 5v operation which will yield an RMS current of 225mA with a peak current of 500mA as shown here • The solenoids are constructed with 30AWG copper with a standard enamel coating • The inside diameter is 0.08inches with an outer diameter of 1/4inch • MagneLab will construct 256 coils at a cost of $500 USD. • Essentially no coil temperature increase, even if left on.

16. Image Processing and Code • Use C++ for Image Processing instead of MATLAB • Cimg.h image processing library/Imagemagik (JPEG images) • Algorithm for Code • Load BMP, JPG, PNG images etc • Obtain color map for the image • Scale the image • Use formula to calculate the intensity of each pixel • Translate intensity level evenly for the required height levels for the pins • Obtain the x and y values for each pixel and store these along with the corresponding pin heights • Code currently loads a BMP image and plots the intensity for the pixels • Compiled executable code size 800KB--Too Big! • Customize Cimg.h, discard unused functions • Compile the C++ code using CrossWorks ARM7 Compiler to convert it into Assembly

17. Power • 120VAC/12VDC, 60W Adapter • Step down converters (12V/5,3.3,1.8V) • 5V rail needs to supply 10A (50W) (Buck regulator) • 3.3V can source up to 1.5A (Buck regulator) • 1.8V rail (LDO regulator), external cap ESR is critical

18. Responsibilities • PCB—Jonathan • CPLD/Verilog—Devon • Processor—Jon, Henry • Board Population—Henry, Jonathan • Image Processing—Khushboo, • Jon • Solenoid Housing—Jonathan • Documentation—Everyone • Driver Circuit—Jonathan, Henry

19. Milestones Milestone I: 1st pcb board assembled and debugged; hardware able to display image via switches; ability to read from Compact Flash Milestone II: 2nd pcb board assembled and debugged; processor/code will be stand alone; first draft of user’s manual; majority of technical reference completed Expo: Processor reading images from Compact Flash, formats it, and sends to CPLD; possible extras

20. Costs Total project budget: $1617.69 EEF Request: $900 Outside funding: Amount   UROP $900 24 Test Solenoids $75 Use of CNC machine in ITLL FREE Item Total Cost Part Number 4 Layer PCB Revisions 1 and 2 $200 N/A Perf. Board $20 8.5”x8.5” Processor (x4) $57.64 TMS470R1A256 Development Kit $399 TMDS-FET470R1B1M Custom Solenoids (x256) $500 Made by: Magnelab, Inc Magnets (x550) $50 Neodymium Iron Boron Compact flash Card 128mb $15.90 CF128 (Kingston) Power adapter 5V,12A $36.96 DTS120500U Components for buck regulator $200 N/A Power Supply and control circuitry Pin Rig – Plastic $30.28 8lb High Density Polyethylene Pin Rig – Plywood $7.49 3/8” x 2” x 4” Pin Rig – Foam Pad $3.49 1’ x 4.5’ Pin Rig - Plexiglass $1.00 6.5”x6.5” Pin Rig – Nuts/Bolts/Spacers $10 N/A Shipping Costs, misc. and taxes $50 Total: $1617.69

21. Risks • Processor Issues • Acquired compiler/assembler/programmer this week • Very limited software support • On chip flash hard to work with • Power converters/regulators • Code Optimization • Image processing may not fit into on-chip FLASH • Magnetic Problems • Increase solenoid spacing or • Downsize 8x8 Array

22. Questions