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Electronics Systems Design For SoC, Wireless, Automotive and Consumer Electronics

Electronics Systems Design For SoC, Wireless, Automotive and Consumer Electronics. TOYOTA. VaST Overview. Headquarters in Sunnyvale, CA Offices in Germany, Japan, Australia, USA (Texas, Michigan, Calif.) Customers in semiconductor, wireless, consumer and automotive electronics

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Electronics Systems Design For SoC, Wireless, Automotive and Consumer Electronics

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  1. Electronics Systems Design For SoC, Wireless, Automotive and Consumer Electronics

  2. TOYOTA VaST Overview • Headquarters in Sunnyvale, CA Offices in Germany, Japan, Australia, USA (Texas, Michigan, Calif.) • Customers in semiconductor, wireless, consumer and automotive electronics • Market-leading technology in simulation performance and accuracy 250 claims in 3 patents, 5+ million lines of code

  3. Wireless and Consumer Devices Multi-CPU architectures processing data, video, voice Automotive Electronics Up to 70 embedded control systems(ECUs) in high end vehicles Electronic System Design is in Crisis • 52% of embedded systems designs are late • 19% are cancelled Source: Venture Development Corp, Q4 2003

  4. Software Re-work Costs $$ “The cost of reworking errors in programs becomes higher the later they are reworked in the process, so every attempt should be made to find and fix errors as early in the process as possible.” - Michael Fagan, 1976 Real-time Software Re-work cost $$$$

  5. Driving the Need for VaST • Faster time-to-market • Narrowing market windows (3-4 months) • Shrinking design cycles (24  12 months) • Increasing design complexity Software the dominating factor • Rapid change, proliferation of personalized products • Less risk • Missed market opportunities  Increases risk of company failure • Acceleration of process and complexity  increases risk of Failure in safety and reliability Failure of each producer in the supply chain to perform • Competitive advantage • Driving engineering excellence to be a competitive advantage

  6. Traditional: sequential development Architectural Specification Hardware Development Fabricate Chip Software Development Integration 24 months * With VaST: the virtual prototype is fast and accurate enough for architecture, hardware and software development Executable Architectural Specification Hardware Development Fabricate Chip Integration 9 months* Software Development Time-to-market advantage *European &Japanese cell-phone manufacturers, actual experience VaST’s Advantage: System-Level Architecture and Concurrent Development

  7. Evaluate architectures of candidate designs using real software applications Architecture Virtual Prototype Hardware development Software development Develop behavioral-level executable specification and verify RTL Design, develop and debug software before silicon or hardware prototypes are available Electronic System Design Process With Virtual Prototypes A system-level approach to complex electronic system architecture, hardware design and software development enabled by Virtual Prototypes

  8. D ROM P ROM StarCore SC1200 Virtual Processor Model ARM926E P1 Virtual Processor Model ARM926E P2 Virtual Processor Model I Cache D Cache StdBus I/F StdBus I/F A H B Buses I Cache D Cache I Cache D Cache StdBus I/F StdBus I/F StdBus I/F StdBus I/F StdBus Bridge StdBus Bridge StdBus Bridge StdBus Bridge Arb. Ctrl DRAM Console 1 Console 2 Memory Block Memory Block UART UART Shared Memory P1 Memory P2 Memory TIMER TIMER INTC INTC Memory Block Memory Block P1 Devices P2 Devices Virtual Prototype Example:3G Cell Phone Controller

  9. Architecture Virtual Prototype Hardware Software Virtual Prototypes: Brain of Electronic System Design • A virtual prototype must be: • Highperformance –to run actual software loads in real time • Accurate – for hardware design and co-verification • Observable – hardware, software and s/w-h/w interactions • Measurable – must have metrics in place to measure results, e.g. power consumption, speed, cost, cache size, etc.)

  10. ComparisonVaST (Virtual Prototype) vs. No Prototype Process VaST Concurrent H/W-S/W Process Risk 88 Units Resour-ces 520 Man-Week Project Period 9 Periods Conventional Sequential H/W-S/W Process

  11. VaST Products: CoMET and METeor CoMET System Engineering Environment Architecture METeor Software Development and Verification Environment Virtual Prototype METeor Firmware Development and Verification Environment Hardware Software

  12. VaST Encompasses the Whole System VaST Buses & Bridges Devices VaST VPMs & Peripheral Devices Structures Architecture Mechanical, Physical Virtual Prototype Sub- systems Evaluation, Exploration Systems VaST VaST Platform Appli- cations Behav. Middleware, Comms Software Hardware RTL Operating Systems Device Drivers Physical VaST

  13. ArchitecturalExploration 8-bit MPU Clock Gen. Serial Comms Interrupt Controller A2D Convert RAM ROM General I/O Bus Interface LowVoltInhibit Virtual bus InterruptTimer EEPROM Virtual Platform Physical Prototype Power Consumption Cost Speed

  14. Competitive Landscape Software development Software, hardware and architecture VaST Virtio Simulation performance 100kips 200MIPS Virtutech Doublewide CoWare Axys Design Mentor (Seamless) Hardware development Low volume, high cost product engineering Accuracy of models

  15. LSI Professional Cameras Printers Copiers Case Study: Toshiba, Canon, Canon, Canon Driver: hook customers with pre-silicon s/w development; reduce time-to-market Driver: 40 new models, narrow market windows, quality, complexity Driver: time to market, complexity Driver: time to market, complexity

  16. Automotive Control Systems

  17. Virtual CAN Sensor Host B Computer Linux Console Virtual CAN Bus Virtual CAN Bus Virtual Platform Virtual Platform Virtual CAN Bus Virtual Platform Virtual SPI Bus StarCore SC1200 ARM926E M32C MIPS 25kf NECv850 M32R MC68HC08 DMAC UART DMAC UART UART DMAC DMAC UART DMAC UART UART UART DMAC Virtual Platform Virtual Platform Virtual Platform Host C Computer SPI Ctrl CAN Controller CAN Controller CAN Controller CAN Controller CAN Controller CAN Controller CAN Controller Timer Timer Timer Timer Timer Timer Timer IntC IntC IntC IntC IntC IntC IntC IntC IntC IntC IntC IntC IntC Virtual SPI Bus SPI Ctrl Auto Timer Video CoDec Auto Timer SPI Ctrl Virtual Host CAN Ctrl Auto Timer Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Memory (CAN Ctrl Device driver Codes) Host Pipe Host USBCAN IXXAT Dev Host CAN Driver Networked Automotive ECU Platforms Virtual CAN Bus Host A Computer •••••• CAN Bus Physical CAN Sensor / Transducer Physical CAN AirBag Virtual Platform CAN Bus

  18. VaST in SoC Design FlowA Closer Look Chip Design Cycle System Arch. Spec. Behavioral  RTL Conversion RTL Design RTL to GDS Fabricate Chip Final integration RTL  Behavoiral Conversion H/W-S/W Co-Verification H/W Team Archi-tectural Verificaton Software development S/W Team Start Time

  19. Hierarchical Hardware Refinement:Behavioral  SystemC  RTL Behavioral Module SystemC Module RTL Module RTL Module under Change

  20. VaST IP Library CoMET Build Comet 5 Virtual Prototype Constructor Standard IP Library (eg Spirit) Behavioral  RTL Translation RTL  Behavioral Translation VaST Tools FlowBehavioral  SystemC  RTL

  21. Policy Specification ISA & Structural Specification Matlab, UML, SystemC, C, C++ Behavioural Modules ISA & Structure Translator CoMET Builder Peripheral Device Generator VPM Generator VPM Specification Graphical H/W – S/W VPM Module Library Platform Configuration S/W Display Bus Library Metrix Stream Selection Metrix Filters and Triggers Target Code (S/W) Peripheral Library 3rd Party Software Debuggers Platform Executable Stream Filter Stream Filter Simulator Initiator Nova Simulator Virtual Prototype Constructor: VPC Peripheral generation Module I/F Specification Simulation Co-processor Peripheral Device Virtual Prototype Constructor Stream Data VPMgeneration Parameterized VPM Library Virtual Prototype Constructor Platformconstruction

  22. Easy to derive schematic for each Level directly from its equivalent Table Specification Tabular Specification Core1 Core1 2D Schematic Specification DMA IntC DMA IntC Core1_D Core1_I Core2_D Core2_I Level 0 BB_Device2 BB_Mem1 BB_Mem2 BB_Device1 SDRAM UART UART Timer Timer SDRAM BB_ ROM1 BB_ ROM2 CAN Level 1 Schematic and Tabular Prototype Specifications

  23. High Level Product Roadmap GA VPM Transformers; Verilog: hw debug; UML/SimuLink sw-hw translator Better support for chip design/ verification CIF Verilog support; FSM support Better visibility and controllability Beta VPM Transformers; Metrix: stream control, filters, charts Better chip design support; Better hw-sw partitioning analysis Software Architecture Hardware Peripheral Builder; Batch mode execution Better UI; Virtual Prototype Constructor; SystemC Easier system-level verification Simplify model creation 9/04 12/04 3/05 6/05 6/04

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