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OpenAccess Gear Functionality:. A Platform for Functional Representation, Synthesis, and Verification. Aaron P. Hurst 1,2 Philip Chong 1 Andreas Kuehlmann 1 Christoph Albrecht 1. 1 Cadence Berkeley Labs. 2 University of California, Berkeley. OpenAccess Gear. Overview.
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OpenAccess Gear Functionality: A Platform for Functional Representation, Synthesis, and Verification Aaron P. Hurst 1,2 Philip Chong 1 Andreas Kuehlmann 1 Christoph Albrecht 1 1 Cadence Berkeley Labs 2 University of California, Berkeley
OpenAccess Gear Overview RTL Synthesis Optimization Framework • OpenAccess Gear (oaGear) is an open source library that extends the utility of the database with a set of common tools and applications • Includes static timer, placer, and GUI • Next release adds extraction, statistical timing, and multiple clock domains • The Functionality package (oaGearFunc) provides a platform for representing, synthesizing, and reasoning about design functionality Tech. Mapping Func. Verification Placement Timing analysis Statistical Timing Extraction
History and Motivation • Initial version developed for a class at Berkeley • Students wrote various algorithms using the software, including tools to perform… • Equivalence checking • Reachable state enumeration • Functional register correspondence • Larger goal is to provide a platform for EDA research that allows… • Evaluation of results within a complete flow • Fair comparisons using standardized benchmarks, algorithms, and timing analysis
Mapper Verilog Liberty Observer Manager ModGraph DdReasoning Engine QueryMod Graph SatReasoning Engine QueryOcc OccGraph Components OA Database
Front-end • Functional descriptions can be imported from… • RTL Verilog • Liberty (.lib) libraries • RTL Verilog parser understands a synthesizable subset of the commonly used 1995 standard • Structural / mapped designs • Hierarchical designs • Behavioral descriptions • Arithmetic operations • Sequential logic • All functional information is synthesized into an common format
left right driver nextState Graph Representation • Functionality is decomposed into a graph • Three node types • Two edge types • AND-INVERTER graphs + sequential nodes
Why Graphs? • AND-INVERTER graphs are familiar to the logic synthesis community • Better than circuits composed of “boxes with pins” because… • Finite and small number of atomic functional units • No special cases • Fast to traverse • Better than an abstract representation of functionality (i.e. a sum-of-products, BDD, etc.) because… • Scale linearly size of design • Preserve topology of circuit
Graph Representation • Efficient memory management • Paged allocation • Garbage collection • Hashing by structural isomorphism • Toolbox of useful algorithms • Transitive fan-in and fan-out • K-way cut enumeration • Equivalent node marking and substitution • Directly incorporated into OpenAccess database • Automatically serialized and unserialized • No data conversion, import/export, etc.
Sequential Elements • All sequential nodes have an input, an output, and store exactly one bit of state • The sequential behavior is specified using one of three available models
oaModBitNet aiRefAppDef = “2” 2 Graphs and OpenAccess • ModBitNets are the working units of functionality • A net is mapped to one TERMINAL node in the graph • The graph reference is stored as an AppDef on the net • Graphs used to describe relationships between nets in modules • The graph structures are allocated and maintained by a Manager object, one per design
oaModBitNet a oaModBitNet b aiRefAppDef = “16” oaModBitNet c aiRefAppDef = “8” aiRefAppDef = “2” 2 6 8 16 Graphs and OpenAccess • An example snippet of Verilog wire a, b, c; assign a = ~(b&c); • a NAND
Graphs and OpenAccess • Two views of the graph are available to the user… • ModGraph • OccGraph • Correspond to the OpenAccess module and occurrence domains • Provide domain-appropriate interfaces for graph ops • getAndLeft(OccRef) vs. getAndLeft(ModRef) • Abstract details of graph-to-net connections • setNetToAiConnection • Include useful functional operations not yet in OA • getAllConnections (get all connected nets across hierarchy)
ModGraph View • Modules and ModGraph elements characterize all instances of that object • All instances implement the same behavior • Functional descriptions “live” in the module domain • ModGraph structure can be modified • Changes affect all instances of that module Module ModInst ModInst ModInst ModInst In the module (folded) view… ModInst Module Module
OccGraph View • OccGraph elements identify one instance of a graph element • The context of where a particular element is instantiated is known • OccGraphs are natural for describing global functional behavior • OccGraphs can not be modified • If one particular instance is to be changed, it must be uniquified into a new type Occurrence OccInst OccInst OccInst OccInst In the occurrence (unfolded) view… OccInst Occurrence Occurrence Occurrence Occurrence Occurrence
Can be simplified using ODC ModGraph is simplified as appropriate Example: Simplifying with an ODC • An ODC (observability don’t care) is a subset of node functionality that is irrelevant due to the subsequent logic • ODCs only apply to a specific instance • Uniquify instance • Simplify new module
Query Objects • There are query objects to simply and efficiently work in a functional representation of the user’s choice • QueryMod • QueryOcc • They callback to the user’s logical ReasoningEngine that implements atomic functional operations • Logical AND • Complementation • Always false / zero function • All graph and OpenAccess hierarchy traversal is performed automatically
myQuery.set(a,aVar); myQuery.get(x); x = aVar | ~bVar Example: BDD of an Output BDD (binary decision diagram) = canonical representation of function What function is being implemented at output x? • Initialize a BDD package • Create a QueryOcc object • Set all inputs • Get the output a b x y • Basis for the included logical equivalence checker
Mapping • In a mapped design… • All functionality is implemented in the leaf cells • Leaf cells are drawn from a set of library cells • Technology mapping removes pieces of the graph and replaces them with functionally equivalent library instances • Final hand-off to native OA data structures • Included SimpleMapper performs a direct mapping from graph elements into three library cells • Better mapper is on the way
Conclusions OA Gear Functionality… • A simple but complete representation for design functionality • Tightly integrated on top of OpenAccess data model • A set of reference tools to take a design from an RTL description to a mapped netlist • The foundation for others to incrementally build and improve a synthesis flow • … with monetary encouragement: IWLS synthesis competition