차세대 SoC (System on Chip) 의 요구사항

1. 차세대 SoC (System on Chip)의 요구사항

2. Darwin’s Philosophy on Wireless Communications?

3. Soft eye?

4. 프로젝터 폰

5. Down Sizing 추세

6. What is System on Chip? Display Driver IC (DDI): STN - TFT - OLED Camera Chipset: CIS - CCD - ISP Connectivity: Wireless LAN - GPS - Bluetooth SoC Processor: AP - MC Modem: GSM/GPRS - WCDMA - CDMA2000 RF/Analog: Rx - Tx - Zero IF - PM RAM: Mobile DRAM - SRAM - UtRAM Smart Card: SIM Flash Memory: Code/Data Storage SIP / MCP

7. 4G (1GMbps~ 100Mbps) Shannon’s law (2.8x / 18m) Mobile Multimedia 3G (CDMA 1xEV) 3,100kbps Full HD (1080i) HD (720p) 2G (IS-95) 9.6kbps 3D graphics D1 QVGA Productivity Gap: Design complexity vs. Moore’s law Power Gap: Design complexity vs. Battery 고성능 및 저전력의 필요성 Design Complexity Moore’s law Battery capacity 1995 2003 2012

8. Sensor network design space Flexibility-Energy Gap 1000 신호처리 ASIC 200 MOPS/mW 100 에너지 효율 (MOPS/mW) FPFA 10-80 MOPS/mW 10 신호처리 프로세서 ASIPs, DSPs 3 MOPS/mW 1 임베디드 프로세서(ARM) 0.5 MOPS/mW 0.1 가용성 Wireless embedded systems design space FPFA : Field Programmable Function Array 6

9. Dual-Core (DSP+ARM) Platform

10. Cell Processor

11. 차세대 SoC의 생산성 증대를 위한 5가지 요구사항 • High Performance • Fast Verification • Small Form Factor • Low Power Solutions • Design-Technology Integration for Manufacturability

12. #. PEs Source: ITRS 2005 draft High-Performance: CMP +NoC Heterogeneous Chip Multi-processor Architecture PE mP Technology Evolution mP Mem Mem PE NoC PE IP IP PE

13. System specification Nielsen’s Law 2x / 12m UML / Java / MatLab Embedded SW 2x / 10m Architecture design SystemC / ADL Moore’s Law 2x / 18m ESL RTL design Verilog / VHDL • Fast Verification:Embedded System Level Complexity Req Grant Addr TLM ctrl1/cmd1/ Data ack0 ack1

14. Mask Costs Technology (nm) Time-to-Market Challenges and Trends Design Costs Shift to • Re-use Strategy at all levels • Higher Level of Abstractions • Software !!! Cost ($M) Increased SW Effort Mask Costs A. Sangiovanni-Vincentelli, DAC 04

15. SDRAM Flash SDRAM 17mm 17mm 3. Small Form Factor • SiP: Mobile Application Processor + Mobile Memory 32MB NAND ~25mm Mobile AP 16MB SDRAM 16MB SDRAM ~35mm 60% Smaller Area EMI Reduction Mobile AP • ▷8-layers of MCP • ▷ Cost reduction by 15%

16. Thermal Aware Architecture Design • Architectural floorplanner • 3D Chip

17. Standby VDD VBP DAC 2004 Active Active VBN VSS Standby 1.2V, 350MHz 1.0V 200MHz 1.5V, 500MHz Multi-Vdd 4. Low Power Solutions Device Architecture Circuit Runtime • MTCMOS • Clock Gating • Multi-Vdd • Parallelization • GALS • Tr Sizing • VTCMOS • Multi-Vt • SOI • High-k Metal Gate • DPM/DVS DVFS • MTCMOS VTCMOS

18. Low-Vth cell High-Vth cell RTL/Vectorless Analysis Electro Migration Multi-Vdd MTCMOS VTMOS DVFS Power Mesh Multi-Vth IR-drop Clock Gating Low Power Techniques for HW Leakage Power Reduction Should consider the power consumption during all design steps Power Analysis / Integrity Dynamic Power Reduction

19. Fault-tolerant algorithm Yield-improving architecture Statistical STA ? Fault Probability Designer’s Intention ? Latency, Power Variation Information Critical Timing,power Vt, Lg, L, t, tILD NA, Tox Vdd, Temp 5. Design-Technology Integration for Manufacturability (DfM) Algorithm Design Architecture Design Logic / Physical Design Mask / Process Design Statistical Analysis Quantum Physics

21. Nano Era SoC has EndlessPossibilities with • High Performance • Fast Verification • Small Form Factor • Low Power Solutions • Design-Technology Integration for Manufacturability