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Logic Design LAB 8

Learn about sequential and combinational logic circuits, memory, SR latch, D flip-flop, synchronization, and edge triggering in this interactive lab. Explore how to implement D-type positive edge-triggered flip-flops using NAND ICs.

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Logic Design LAB 8

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  1. Logic Design LAB 8 授課老師：伍紹勳課程助教：邱麟凱、江長庭

  2. Outlines • Sequential logic circuits • Memory and Clock • SR latch • D Flip-Flop • Lab

  3. Sequential logic circuits • Combinational logic circuits • depends only on current inputs • Sequential logic circuits • depends on past and current inputs Memory and Clock!!

  4. SR Latch • SR Latch (Memory) • Steady state results 0 1 0 1 R R R R 1 Q Q Q Q 0 1 Q’ Q’ Q’ Q’ S S S S 0 Q 1 Q’ 1

  5. Clock • When to set and reset • How to synchronize devices with memory • Positive (rising) edge triggered • Negative (falling) edge triggered time

  6. Flip Flops • Input type • SR、D、JK、T • Trigger type • Rising(positive)-edge • Falling(negative)-edge

  7. D-type positive edge triggered FF 1 SR Latch R 2 5 Q Clock 6 Q’ 3 S 4 D

  8. D Flip Flop Clock: 0->1 Clock = 1, D: X->X’ Clock = 0 X X->X X X’ 1 1->X’ R R R S = X, R = X’ ⟹ Set the latchas X S, R = 1 ⟹ Hold S, R will not change with D 0->1 1 0 Clock Clock 1->X Clock X 1 S S S X’ X’->1 X’ X X X->X’ D D D

  9. Lab • Today’s target: D-type positive edge triggered Flip-Flop • IC： 7400 (NAND) x 2、LED x 1 3 How to realize three-inputs NANDs with two-inputs NANDs? How to realize three-inputs NANDs with two-inputs NANDs?

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