D0525 Project

1. D0525 Project Receiver for Quantum Encryption System High Speed Digital Systems Laboratory Summary Presentation Part A Winter 2007 By: Dattner Yony & Sulkin Alex Supervisor: Yossi Hipsh& Eli Shohan Quantum encryption system - receiver.

2. Reminder : The overall system. • The system is a communication system, like many others – but what makes this particular system “unique” that would require that much attention in the form of three whole separate projects (transmitter, synchronization and receiver team )? • The answer is security. • Quantumencryption using the BB84 protocol has been mathematically proven to be 100% securein an idealworldwithout noise. This is mainly due to the uncertainty principle regarding photons. • Generally speaking the purpose of this electro-optical communication array is to successfully encrypt a single photon, to transmit it via a secure channel to the receiver which is responsible for successful decryption of the photon and to keep track of the photons received. Quantum encryption system - receiver.

3. Transmitter unit (encrypt) Synchronization unit Sync optical line Data optical line Receiver unit (decrypt and count) Reminder : The overall system. • The communication system is dived into three main sub-systems: • The transmitter - is responsible for the encryption of the photon and its transmissioninto the fiber optic data line. • The synchronization unit – serves as a link between the transmitter and the receiver, simply speaking its role is to let the receiver know when he should be expecting a photon that was transmitted. • The receiver – is responsible for receiving the signal from the sync unit and use it in order to receive the photon from the data channel (also known as quant channel). Quantum encryption system - receiver.

4. Reminder : The overall system. • A more detailed view of the overall system can obtained through the following schematic: Quantum encryption system - receiver.

5. Reminder : The overall system - interface.

6. Reminder : Modes of operation • Let us briefly recall the various modes of operation of the system: • STAB – in this mode we calibrate the interferometers that precede the Geigers , this process is not directly related to the receiver. During this stabilization high energy photons are sent to the receiver. In order not to damage the Geiger, we block it. • SYNC – before we are ready to receive the data photons we must synchronize the system, details to follow. • QUANT – this is the normal operation of the system where the transmitter transmits data photons and we receive them (available only after STAB and SYNC have been completed). Quantum encryption system - receiver.

7. Reminder : The Geiger. • The Geiger is an electro-optical device that enables us to detect the incoming photons, it has two purposes: 1) It is able to detect single photons. 2) It converts the optical data to electrical. • The Geiger is actually a very unstable photo diode that avalanches with the impact of a single photon. Principal of operation: Quantum encryption system - receiver.

8. Reminder : Geiger – continued. • The output of the Geiger when there is a photon impacting: • The output of the Geiger when there is no photon impacting: • The Geiger is opened when we provide it with an additional reverse voltage of 10V that comes from the sync unit (this pulse is 3ns wide). Quantum encryption system - receiver.

9. The receiver. Quantum encryption system - receiver.

10. The receiver - continued. • The inputs and the outputs of the receiver are: Quantum encryption system - receiver.

11. PCB – block diagram. Quantum encryption system - receiver.

12. SYNC mode. • The synchronization process is divided into two parts: • The sync unit performs rough synchronization with their DDLs – shifting their sync pulse until a detection of the data photon occurs . • The receiver unit performs delicate synchronization with their DDLs – shifting their pulse until it coincides with the desired area inside the sync pulse (close to the left shoulder) • After the both parts of this process are completed than we are ready to receive the photon – and to switch to the QUANT mode. • We present two flow charts that explain the both parts of the SYNC mode in more detail: Quantum encryption system - receiver.

13. QUANT + STAB modes. • The QUANT and STAB modes are periodically intertwined , after every QUANT photon that is transmitted we block the receiver ( and the Geiger) than transmit ten STAB photons that stabilize the interferometers. The STAB photons are more energetic then the QUANT photons – may damage the Geiger if not blocked. Quantum encryption system - receiver.

14. The components. Quantum encryption system - receiver.

15. The components - continued. • The original plan was to use ECL only parts, but as you can see we needed a few TTL devices for two main reasons: • The counters at the computer receive TTL levels. • For the stretcher we need a relatively large range of delay (~30ns) – this can be achieved by DDL TTL. • The very first thing we need to verify is the voltage compatibility between our components: Quantum encryption system - receiver.

16. The components - continued. • Notes: • This device (MUX 2:1) comes with OLS (Output level selection) that allows us to control its V_ol in 5 steps – when connecting the OLS pin to V_cc we get the numbers in the table. • The comparator input is NOT ECL but it is an analog input that is restricted by the minimum and maximum voltages allowed in its input. So the minimum is -0.2V and the maximum 3.1V, given that V_cco=5.2V (output stage source). • Here we have a problem: the driver’s DC level is too high and its swing is too low. Fortunately, the receiver’s minimum differential input sensitivity is 150mV. All we need to do is to put an attenuator between the comparator and the Buff 1:2 to reduce the DC level. (From 2135mV to about 1880mV). Quantum encryption system - receiver.

17. The components - continued. • For TTL parts we will check the voltage level compatibility by assuring are positive. • We build another table for the TTL parts: • Notes: • Although in this case – we don’t believe this will pose a big problem because : • The for 3d7408-1 is given when - in practice we have so should rise a little giving us larger . • Even if is still not positive but is good enough for our application. Quantum encryption system - receiver.

18. The components - Comparator. • is the negative reference voltage. • is the positive reference voltage (in our case – the input). • are on-chip termination pins ( ). • are resistors that control the voltage level ( is a variable resistor). • is some reference voltage ( for example). • All the capacitors ( ) are standard cooling capacitors. Quantum encryption system - receiver.

19. Comparator - continued. • Note that in order to get a wider range of the input voltage we select but the output is standard differential PECL so . • are standard receiver ECL termination resistors. • is also a variable resistor used to determine the level of hysteresis we require ( this must be based on the study of Geigers output characteristics). • The amount of hysteresis as a function of : Quantum encryption system - receiver.

20. The DDL (ECL). • The DDL cascade connection feature: • The DDL-ECL (MC100EP195) has an option that allows us to connect several DDLs in a cascade configuration. In order to save FPGA control lines we choose this cascade configuration for our two serial DDLs. • Step: . • Delay range: . Quantum encryption system - receiver.

21. The BALUN. • The balun we use is a passive self-made circuit; we use it in order to feed AMP1. On each PCB we have two such baluns, one for the AMP1 and the other used as TP1: From Buff 1:2 ECL Quantum encryption system - receiver.

22. Power. • According to the power dissipation of the parts we suggest the use of ON-Semi’s NCP1086 as a regulator both for the 5V and the 3.3V supplies. • The NCP1086 linear regulator provides 1.5 A at 3.3 V or adjustable output voltage. We will also use it as a regulator for our voltage. Quantum encryption system - receiver.

23. The DFF timing constraints. • First we extract the following timing data from the DFF’s datasheet: • Since are measured with 50 ohm termination to Vtt – if we take into account the C_in of the next component – we will get larger . • We have to make sure that D pin will be stable before clk rise and after clk rise. • Since we have a minimum value for we take care and take for our calculations. Quantum encryption system - receiver.

24. The DFF timing constraints - continued. • The figure shows the relevant part of the logical schematic; you can see the DFF and three separate paths (red, blue and pink). • Remember that the red one has to be stable before and after the blue and pink ones. • The width of the red pulse (coming from the Geiger – indicates the detection of the photon) is well over , otherwise – the sampling is not possible. • We just have to make sure that the pink and the blue rise arrive inside the “logical zone” of the red pulse: Quantum encryption system - receiver.

25. The DFF timing constraints - continued. • We notice that for the pink path, there is no problem making it into the “logical zone” because there are two serial DDLs in the way .Both the fine delay resolution and the delay range allow us to make it to the “logic zone” (that is exactly the delicate stage of the synchronization process done by the receiver team). • Now we have to check the blue path, when Mix_sel_1=HIGH. That happens when we are in the coarse synchronization stage (done by the sync team). That is when we are required to sample the output of the Geiger as it is, not with our second window (which is much narrower). • It is clear that: Or: • We can see that which guarantees the setup condition is fulfilled. • This means that in order for the hold condition to be fulfilled, the Geiger’s output must have: . • That is, if the width of the Geiger’s output is large enough then both setup and hold condition will be fulfilled. Quantum encryption system - receiver.

26. The electrical diagram.

28. Conclusion. • In Part A we were introduced to: • The overall system + modes of operation. • Receiver structure. • The block diagram of the receiver’s PCB. • The electrical parts. • Power considerations. • Timing. • The electrical diagram. • In Part B we will see : • Control interface. • FPGA programming. • Logical simulation. • Stack-up design. • Signal integrity issues + HYPERLYNKS simulations. Quantum encryption system - receiver.