HSDSL Lab final presentation CORDIC implementation on FPGA winter 2013-14

1. HSDSL Labfinal presentationCORDIC implementation on FPGAwinter 2013-14 supervisor MoniOrbach Students: Or Rotem Malachi Levi

2. overview • Project process: • Understanding the algorithm • Architecture examination • Golden model – C lang • Simulation environment buildup • Coding • Simulation • Synthesis

3. Theory

4. Block diagram בלוק לחישוב σ סימן התוספת בלוק לחישוב σ סימן התוספת בלוק לחישוב התוצאה בלוק לחישוב התוצאה

5. compare • This block compares the current angle with the desired one • Increment the current angle according the result

6. calculate • Perform the matrix calculation • Uses the result from the compare block

7. LUT • Lutis Decimal at it’s source – conversion to binary took place according to architecture needs

8. Simulation environment

9. Synthesis • Chip: Cyclonll • Synthesizer: quartos 12.1

10. Synthesis issues • The design was modified for resources optimization • Pin planner was done and led was programed to show calculation result – counter clock

11. Synthesis statists • The resources usage is approx. the same as the Altera build in block

12. Clk frequency ~120MHz • Limited by longest path • Was improved dramatically over the process • The pipeline is improving the frequency by ~30 times • System Latency is 30 clk cycles

13. Pipeline appearance

14. Usage of the cyclon2 logic and cell and registers

15. Cyclone 2 vs cyclone 3

16. Signal Tap • The results was checked and found correct • Expected vals came from the simulation environment • This is the way to test the “real” system output

17. Summery & conclusions • Architecture • Simulation environment • High level coding not always come in one hand with FPGA • Other synthesis programs might give better results • importance ofclk frequency

18. end

19. Appendix – the codecalculate

20. Appendix – the codecompare