1 / 14

Data Acquisition ET 228 Chapter 14.4-8

Data Acquisition ET 228 Chapter 14.4-8. Multipling DACs 8-bit DAC the DAC-08 Microprocessor Compatibility AD558 Microprocessor-Compatible DAC Serial DAC. Data Acquisition ET 228 Chapter 14.4-8. Voltage Output DACs Figure 14-7 on Page 413 Equations

libra
Download Presentation

Data Acquisition ET 228 Chapter 14.4-8

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Data Acquisition ET 228Chapter 14.4-8 • Multipling DACs • 8-bit DAC the DAC-08 • Microprocessor Compatibility • AD558 Microprocessor-Compatible DAC • Serial DAC

  2. Data Acquisition ET 228Chapter 14.4-8 • Voltage Output DACs • Figure 14-7 on Page 413 • Equations • VO =Rf • IOut = Rf • (1/2n • VRef /R) • D == Rf • I0 • D • VO = Rf • I0 • D = V0 • D • Where V0 = Rf • I0 = VRef/2n • Multiplying DAC • Output Voltage is a multiple of VRef • Equations • VOut = Constant • VRef • D • Constant = Rf • (1/2n • 1 /RRef) = Rf//(2n R) • Figure 14-7 on 413 • Review on page 429 • Compare VOut on Fig 14-7 with Rf = 10K-ohms to Fig 14-7 with VOut with Rf = 2.5Kohms

  3. Data Acquisition ET 228Chapter 14.4-8 • 8-Bit DAC: the DAC-08 • Characteristics • Low cost • Fast • Multiplying DAC • 8-Bit DAC: the DAC-08 • Figure 14-8 & 9 on pages 415 & 419 • Terminals • Power Supply Terminals • Reference (Multiplying) Terminal • Digital Input Terminals • Analog Output Terminals • Uniplor Output Voltage • Bipolar Output Voltage

  4. Data Acquisition ET 228Chapter 14.4-8 • 8-Bit DAC: the DAC-08 • Power Supply Terminals • Pins 13 & 3 • + 4.5 to +18 volts • 3 is the negative • 13 is positive • Require 0.1 and 0.01 F shunting capacitors • See 14-8 • Reference Terminal • Can have Positive or Negative references • Pin 14 is for a positive reference voltage • Pin 15 is for negative reference voltages • Current reference IRef can easily be adjusted • Range of 4A to 4 mA with a typical value of 2 mA • IRef = VRef/Rref

  5. Data Acquisition ET 228Chapter 14.4-8 • 8-Bit DAC: the DAC-08 • Digital Input Terminals • Pins 5 - 12 • Pin 5 is the MSB (D7) • Pin 12 is the LSB (D0) • Acceptable Voltage Levels • TTL or CMOS • Logic “0” is voltages less than 0.8 V • Logic “1” is for voltages of 2.0 or grater value • Analog Output Terminals • Current Resolution = I for the LSB = I0 • = 1/2n • VRef /R • IOut = Current Resolution • D = I0 • D

  6. Data Acquisition ET 228Chapter 14.4-8 • 8-Bit DAC: the DAC-08 • Analog Output Terminals • Ifs = Current Resolution • 255 = I0 • 255 ____ • IOut = Ifs - IOut • Example Problems • 14-8 on page 416 • 14-9 on page 417 • Unipolar Output Voltages • Configured per Figure 14-8 with external OP-Amp • Voltage Resolution of the LSB = Rf • (1/2n • VRef /RRef)

  7. Data Acquisition ET 228Chapter 14.4-8 • 8-Bit DAC: the DAC-08 • Unipolar Output Voltages • Configured per Figure 14-8 with external OP-Amp • Voltage Resolution of the LSB = Rf • (1/2n • VRef /RRef) • VOut = Voltage Resolution • D = Rf • (1/2n • VRef /RRef) • D • Example Problem 14-10 on page 417 • Bipolar Output Voltages • Configured per Figure 14-9 with external OP-Amp _____ • VOut = (IOut - IOut)Rf • Example Problem 14-11 on page 418

  8. Data Acquisition ET 228Chapter 14.6-8 • Microprocessor Compatibility • Key Aspects • Interface Principles • Memory Buffer Registers • DAC Selection • Interface Principles • Programmers view a DAC • An addressable register • Usually a a write only register • Digital information only goes into the DAC • Programmers view of a ADC • An addressable register • Usually a a read only register

  9. Data Acquisition ET 228Chapter 14.6-8 • Microprocessor Computability • ADC & DAC Memory Buffer Registers • Both have two states • Transparent • Latching • Transparent • Connected to the data bus • An ADC can be read when in this state • A DAC can be written too when in this state • Latching • Connections to data bus is in a high impedance state (High Z) • Register of a DAC holds last value written to it when the connection was in the Transparent State

  10. Data Acquisition ET 228Chapter 14.6-8 • Microprocessor Computability • ADC & DAC Memory Buffer Registers • Latching • Register of an ADC cleared in preparation to hold the next analog to digital conversion which be read by the bus when the connection goes back to the Transparent State • ADC or DAC Selection Process • Two Stage operation • The address bus is used to select a specific converter • The Chip Enable signal is sent to all DACs or ADCs • Only the converter that was addressed responds to the Chip Enable signal • Figure 14-10 _________________ • Key Points: Address Decoder & Read/Write signal

  11. Data Acquisition ET 228Chapter 14.6-8 • AD558 Microprocessor-Compatible DAC • Key Aspects • Characteristics • Power Supply • Digital Inputs • Logic Circuit • Analog Output • Characteristics • Reference • 8 Bit DAC Figure 14-11 on page 422 • On circuit voltage reference ________ _________ • Dual Signals required for activation - CS and CE • Op Amp included for voltage output • Output voltage ranges (FSRs) 0 - 2.56V to 0 - 10V

  12. Data Acquisition ET 228Chapter 14.6-8 • AD558 Microprocessor-Compatible DAC • Power Supply • Vcc 4.5 to 16.5V - Pin 11 • Pin 12 - digital ground • Pin 13 Analog ground • One or both must have a 0.1 F connected to Vcc • Digital Inputs • Two States • Transparent • Latching • Pins 1 - 8 • D0 to D7 respectively • TTL or Low Voltage CMOS levels • Logic 1 --- 2.0V or greater • Logic 0 --- 0.8 V or lower

  13. Data Acquisition ET 228Chapter 14.6-8 • AD558 Microprocessor-Compatible DAC • Logic Circuitry ________ _________ • Dual Signals required for activation - CS and CE • 0 logic levels required to activate • Pins 9 and 10 respectively • Analog Output • Output between pins 16 and 13 • Pin 15 is for remote voltage sensing • Used to minimize IR drops in long lead lines • Pin 14 is the Output Voltage range selector • Op Amp included for voltage output • Full scale voltage ranges 0 - 2.56V to 0 - 10V • Tied to Pin 16 yields 0 -2.56 range • Actually 0 -2.56V - 0.01V/ LSB = 2.55V

  14. Data Acquisition ET 228Chapter 14.6-8 • AD558 Microprocessor-Compatible DAC • Analog Output • Pin 14 is the Output Voltage range selector • Tied to Pin 13 yields 0 -10 range • Actually 0 -10.000 - 0.0389V/LSB = 0- 9.961V • Serial DAC • Like a parallel DAC But data is shifted into the DAC one bit at a time • See Figure 14-13 Reference • Actually loaded into a shift register then into DAC Register • Serial data line and clock lines used -- Pins 6 & 7 • A logic 0 level on pin 5 loads the shift register's content into the DAC register

More Related