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8051 Instruction set and Programming

8051 Instruction set and Programming. Introduction Programmer’s Model Addressing Modes Instruction Set Examples and Exercises. Valve. Analog Mux. Analog sensor. DAC. ADC. Stepper motor. Interrupt. Timer Counter. Digital sensor. µp. D mux. Digital Mux. Digital Actuator.

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8051 Instruction set and Programming

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  1. 8051 Instruction set and Programming • Introduction • Programmer’s Model • Addressing Modes • Instruction Set • Examples and Exercises

  2. Valve Analog Mux Analog sensor DAC ADC Stepper motor Interrupt Timer Counter Digital sensor µp D mux Digital Mux Digital Actuator Information flow in Real time System Alarm Annunciator Binary Switches Digital Mux Memory I/O System

  3. SUB SYSTEMS - ANALOG SENSORS - DIGITAL SENSORS -BINARY SWITCHES MUX µP + Memory + I/O - DAC + Valve - Stepper Motor -Digital Actuator - Alarm Annunciator D MUX

  4. 8051 Microprocessor • General Facilities • 8 bit CPU • On chip clock oscillator • 4 KB of ROM (Program memory) • 128 bytes RAM (Data Memory) • 21 Special Function Registers(SFR) • 32 I/O lines (Ports P0 to P3) • 64 KB address space for external data memory • 64 KB address space for program memory • 2- 16 bit timer/counter • 5 source interrupt structure

  5. Full duplex serial port • Bit addressability • Bit processing capability • MCS-51 compatible chips • 8031 – Romless version – 4KB ROM not available • 8751 – EPROM version – 4KB EPROM • 8052- (8 KB ROM + 256 byte Data memory)

  6. Programmer’s Model • Resources used in programming • Memory • Special Function Register • Program status word • Memory – • Program Memory -4 KB on chip ROM 60 KB External RAM or 64 KB External RAM • Internal Data memory – 256 bytes 128 bytes Internal Data RAM 21 SFRS 64 KB

  7. 0FFF 0000

  8. Internal Data memory - 128 bytes internal data RAM is divided into 32 bytes - 4 banks of Register R0-R7. - Register Bank selected by using 2 bits RS0 & RSI in PSW. - 16 bytes direct addressing bits (total 128 bit addresses). - 80 bytes general purpose RAM. 00-1FH 20 – 2FH 30 – 7FH

  9. Internal RAM Partitioning

  10. 80- FFH Special Function Registers (SFRs) • SFRs used to program different resources of 8051. • Times/counters , serial ports, interrupts. • Some SFRS are bit addressable. • SFRs are B reg, ACC, PSW DPTR (DPH , DPL) , SP - P0 , P1, P2, P3 – Port Register - SCON, SBUF - for serial I/O - TMOD, TCON, TH1, TH0, TL1, TL0 – For Timer / Counter - IP, IE – for interrupt control - PCON – Power Control Reg.

  11. Memory Map of 8051 FFFF External (60 KB) FFFF 64 KB 1000 Over lapped Space 0FFF 0FFF FF 80 7F Internal (EA = 1) (4 KB) External (EA = 0) (4 KB) SFRs Internal Data RAM 0000 00 0000 0000 External Data Memory Internal Data Memory Program Memory

  12. 7 FH 30 H 2 FH 20 H 1 FH 18 H 17 H 10 H 0FH 00H 07H 00H 127 48 32 24 16 8 00 80 bytes Byte Addressing – General Purpose Direct Addressable bits 16 bytes 32 bytes Internal Data RAM

  13. Program Status Word 7 6 5 4 3 2 1 0 • CY- (PSW-7)- Set if operation results in carry out of (during addition) or a borrow in to (during subtraction) the higher order bit of the result otherwise CY in reset. • 0F FH + 1 = +1 1 • 02H – 5 = 1 0 1 1 User Flag 0 Reserved bit Carry Borrow

  14. AC- (PSW.6) - is set if operation results in carry out of Lower Nibble (during addition) to Higher Nibble or borrow from Higher Nibble to Lower Nibble (during subtraction) otherwise it is cleared. ( Used For BCD addition/Subtraction) • RS1 , RS0 (PSW.4, PSW.3) - represent the current register bank in the internal data RAM selected. PSW SFR is bit addressable. RS1 RS0 0 0 - Bank 0 0 1 - Bank 1 1 0 - Bank 2 1 1 - Bank 3 Default - Bank 0 • OV – Overflow (PSW.2) is set if operation results in carry in to the higher order bit of result but not carry out of higher order bit or vice versa. OV has significant role in two’s compliment arithmetic, since it becomes set when signed result can’t be represented in 8 bits.

  15. Example (1) - = +127 + 0 0 0 0 0 0 0 1 OV set Carry in to MSB but not out of MSB Result = -ve no. Example (2) - 1 + -1 = -2 -1 = - 1 = If you consider CY is 8th bit then the result is -2 only. CY 1’s compliment = 0 0000 0001 +1 = 0 0000 0010 1 1 1 1 1 1 1 0 Carry Carry OV in not set Sign of result is correct. CY is set

  16. P-odd parity (PSW.0) – is set if no. of ones in the accumulator is odd otherwise it is cleared (even parity). • User flag 0 and Reserved bit are for internal use of chip. Not available to programmer.

  17. OperandTypes • Bytes - Unsigned 8 bit nos. , ASCII code etc • Short Integer – Signed number. • Bits – are represented in Bit addressable RAM. - 128 bits within internal data RAM. - 128 bits within SFR may be addressed directly. • Separate instructions for bit processing. CY is used in bit processing as ACC. • 16 bit operations are not facilitated. Thus 16 bit operand can’t be addressed. • In MUL instruction (Multiplication) MUL AB Operand 1 - Stored in ACC. Operand 2 - Stored in B reg. Result in 16 bits stored in B reg. (higher bytes) and ACC (lower bytes).

  18. In Div instruction (DIV) DIV AB Operand1 - Stored in ACC (8 bits) Operand 2 – Stored in B register (8 bits) • A/B is performed Result – Quotient – Stored in ACC Remainder – Stored in B register

  19. Addressing modes Immediate Addressing Register Addressing Direct Addressing Register indirect Addressing Base Register plus index register indirect addressing.

  20. Immediate Addressing Operand on which operation to be performed is part of instruction. Example: - MOV Rn, # data (n = 0 to 7) (Rn) data - ADD A , # data (A) (A) + data - ADD A , # 0FH

  21. Example:- ADD A, # 0FH Program Memory + E0H (ACC) 1FH Internal Data Memory Reg. Bank R1 R0

  22. Register Addressing • Register R0 – R7, A, B, DPTR and SFR register may be accessed. Reg. bank may be selected by RS1 RS0 bits of PSW. Example – MOV A , R2 (A) (R2) ADD A , R3 (A) (A) + (R3) DEC R2 (R2) (R2) - 1 Program Memory E0H ACC 24 H 02 01 00 R2 R1 R0

  23. Direct Addressing • Address of operand is specified in the instruction. - may be byte operand or bit operand. • Direct Addressing of byte operand may be. - Lower 128 byte of Internal Data RAM i.e Address 00 to 7FH - Special Function Register. • Direct bit address provides operation on - 128 bit subset of Internal Data RAM (20H to 2FH) - Subsets of SFR address space (80H to FFH) Out of 21 SFR’s , 11 SFRS are direct bit addressable. Note – Only Internal data RAM space can be directly addressed.

  24. Example – LDA 2400 H ACC 2400 H 30H R0 R1 R2 LDA 2400H 0000

  25. Indirect Addressing • Address of operands not specified directly. Instead , address of operand is specified as content of register mentioned in the instruction. • For internal data RAM space – Indirect addressing using register R0 or R1 is possible.

  26. Example – MOV A, @ R0 (R0 has the address of operand) (A) ((R0)) A E0H 33H 2 52 H 1 00 R0

  27. For external data RAM , 16 bit register DPTR may be used to access any location within full 64 KB memory • R0 and R1 may be used for up to 0FFH external data memory space. • Instruction is MOVX Example - MOVX A, @ R1 (A) ((R1)) MOV DPTR, # 0240FH MOVX @ DPTR , A MOVX A, @ DPTR (( DPTR)) (A) (A) ((DPTR))

  28. E0H A 2 1 240F DPH DPL 83H 82H DPTR External Data RAM SFR

  29. Base Register Plus Index Register Addressing • Used to access program memory. • Operand is not specified directly. • Operand Address = (Base Reg) + (Index reg.) Base Register – DPTR or PC – 16 bit register Index Reg – ACC Thus Operand Address = (A) + (DPTR) or (A) + (PC) as specified in the instruction. • Instruction is MOVC C – means program memory access Example- MOVC A, @ A+DPTR (A) ((A) + (DPTR) • Used for reading already stored arrays as part of program memory

  30. Example:- ARRAY : DB 3FH, 39H, 0FH, 37H ----- MOV R5, #0AH MOV DPTR, #ARRAY MOV R3, A L1 : MOVC A, @ A + DPTR ------------ ----------- ---------- MOV A , R3 INC A DJNZ R5 , KK1

  31. 0502 0501 0500 MOVC A, @ A + DPTR Program Memory 3 2 E0H A 1 + 0500H 1 DPH DPL 83H 82H DPTR

  32. DataTransferInstructions • General Purpose Data Transfer • Accumulator Specific Data Transfer • Address Object Data Transfer

  33. General Purpose Data Transfer • . MOV – byte or bit transfer • . PUSH - byte to stack • . POP - byte from stack (Flags not effected unless PSW in being modified)

  34. MOV <dest.> <src> Move byte variable • MOV Rn, # data – Immediate Addressing • MOV A, # data - Immediate Addressing • MOV Rn, A - Register Addressing Note - MOV Ri , Rj – Not allowed • MOV A, Rn – Register Addressing • MOV A, Direct – Direct Addressing • MOV Direct , A - Direct Addressing • MOV Direct , Rn - Direct Addressing • MOV Rn , Direct - Direct Addressing • MOV Direct , Direct - Direct Addressing

  35. MOV @Ri , A – Indirect Addressing • MOV A , @Ri -Indirect Addressing • MOV Direct, @Ri – Direct + Indirect • MOV @Ri, Direct – Direct + Indirect (Ri = Ro or R1) • MOV Direct, # Data - Direct + immediate • MOV @ Ri , # Data – Indirect + immediate

  36. MOV < dest. bit> <Src. bit> • Move bit variable. • Carry acts as ACC for bit operation . • MOV C , bit (C) (bit) • MOV bit , C • PUSH Direct (SP) (SP) + 1 ((SP)) (Direct) • POP Direct (Direct) ((SP)) (SP) (SP) - 1

  37. Accumulator Specific Data Transfer • XCH – Exchange data between A reg. and byte source operand • XCHD –Exchange lower Nibble in A with Lower Nibble of source operand (Indirect Addressing). • MOVX – Data transfer between external data memory and A register(Indirect Addressing). External address in DPTR. • MOVC – Move byte from program memory to A. (Base Reg + Index reg. indirect addressing) • XCH A, <byte> XCH A, Rn – Register Addressing XCH A, direct – Direct Addressing XCH A, @Ri – Indirect Addressing

  38. XCHD A, @Ri (Ri = R0 or R1) • MOVX < dest. Byte> <src. Byte> MOVX A, @ Ri MOVX A , @ DPTR MOVX @ Ri, A MOVX @ DPTR , A • MOVC A, @A + DPTR (Move code byte) (A) ((DPTR)+(A)) • MOVC A, @A + PC (A) (( PC) +(A))

  39. Address object Transfer Move 16 bit address as immediate data to DPTR MOV DPTR, # Data16

  40. Arithmetic Instructions Flags are affected • Operations – Add , Subtract , Multiply, Divide, Increment, Decrement. Only 8 bit operations are permitted. • ADDITION:- ADD A, (src. Byte) - Add (A) (A) + (Src.) • ADDC A, (Src byte) Add with carry (A) (A) +(Src) + (C) • Register Addressing- ADD A, Rn (A) (A)+(Rn) ADDC A, Rn (A) (A)+(Rn)+(C)

  41. Direct Addressing src = direct address (A) (A)+(direct)+(C) (A) (A) + (direct) • Indirect Addressing src = @Ri (R1 or R2) (A) (A)+((Ri)) (A) (A) + ((Ri)) + (C) • Immediate Addressing src = # data (A) (A) + data (A) (A)+(C)+data • INCREMENT • INC <byte> INC A, INC Rn , INC @Ri, INC direct • INC DPTR is additional instruction (DPTR) (DPTR) + 1

  42. SUBTRACTION SUBB , DEC Decrement Subtract with Borrow • SUBB A, <Src. byte)> (A) (A) - (Src) (C) Register –Src = Rn Indirect – Src = @Ri ( i =0 or 1) Direct – Src = direct Immediate- Src = # data SUBB A, @Ri – (A) (A)-((Ri)) – (C) DEC <byte> <byte> = A, Rn ,@ Ri ,direct DEC A , DEC Rn , DEC @ Ri , DEC direct

  43. MULTIPLY MUL AB (A) - Operand 1, (B) – (Operand 2) After operation (A) - lower order byte (B) - Higher order byte • DIVIDE DIV AB (A)/(B) quotient in A remainder in B of Result

  44. DA A (Decimal Adjust Accumulator for addition) If two BCD numbers (in packed BCD format) are added using ADD or ADDC instructions then to represent the result in BCD. DA A instruction is used, Algorithms is- • If value of lower Nibble in ACC > 9 or if AC Flag is set then 6 is added to ACC. • Now after (1), if value of higher Nibble is greater than 9 or if CY Flag is set then 6 is added to higher Nibble of ACC.

  45. Example :- A & R3 have BCD number A = R3 = A= R3= After ADD A, R3 instruction. A = Not in BCD DA A instruction (1) Lower Nibble = 12 i.e > 9 (A) (A) + 6 + 0110 = (2) Higher Nibble = 9 , CY=0 So no action – Result 92 is BCD number.

  46. LOGIC INSTRUCTIONS Single operand Instructions • Clear CLR A (A) 0 CLR bit (bit) 0 CLR C (C) 0 • SET SETB C (C) 1 SETB bit (bit) 1 • Compliment ACC CPL A , (A) (A) • Compliment bit CPL bit , (bit) (bit) CPL C , (C) (C)

  47. 1 0 7 ROTATE ACCUMULATOR INSTRUCTIONS • RL A Rotate ACC Left by 1 bit • RLC A Rotate ACC Left through Carry. 1 0 7 6 CY

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