Simplifying MSO-based debug of designs with Xilinx FPGAs

1. Simplifying MSO-based debugof designs with Xilinx FPGAs

2. 1) Route nets out to FPGA pins • 1 signal per FPGA pin; usually pin limited • Requires design change to view new signals • Manual management of physical and logical signal mapping to MSO digital channels and labels • Equal time investment for each iteration FPGA Agilent 9000 or 7000 Series Pins ExternalMSO Probe points

3. Manual Setup of Physical Connection Single pin example Pin 6 of the FPGA Goes to pin 10 of the mictor connect Connects to pod 1 channel 8 of the MSO FPGA Probe footprint Oscilloscope

4. Manual Setup of Signal/Bus Names on MSO Determine to which connector pin it was routed Look at schematic Determine which logic channel is connected to that pin Hand type eachname in MSO for every signal routed to debug pins Signal namein FPGA Probe footprint FPGA Oscilloscope

5. Incremental Real Time Internal Measurements …without: Stopping FPGA Changing the design Modifying design timing Quick MSO Setup FPGA pins to MSO digital channels Signal and bus names World’s First (& only) Integrated FPGA Oscilloscope Application MSO FPGA Dynamic Probe Application

6. MSO FPGA Dynamic Probe Application • Options for Xilinx • With 9000 Series MSOs • With 6000/7000 Series MSOs

7. Datasheets, Design guide, FAQ, & Resource Calculator • Options for Xilinx • With 8000 Series MSOs www.agilent.com/find/8000-Xilinx • With 6000 Series MSOs www.agilent.com/find/6000-Xilinx

8. FPGA Dynamic Probe SW application supported all Agilent MSOs Probe core output USB or Parallel Control access to new signals via JTAG JTAG FPGA Dynamic Probe for Xilinx PC Board FPGA Insert ATC2 core with Xilinx Core Inserter ATC2

9. Agilent Trace Core (ATC2) ATC2 Output to FPGA pins for debug • Up to 64 signal banks • All banks have identical width (4 to 128 signals wide) 4 - 128 4 - 128 4 - 128 Selection MUX 4 -128 4 -128 clk clk Up to 16 digital channels on MSOs JTAG Select Change signal bank selection from MSO`

10. Core Types for MSO • State Core (most common usage) • Best for functional debug in one time domain • Minimal impact on timing • MSO timing (asynchronous measurement) • Measured on each FPGA clock cycle • State trigger • Trigger on pattern + clock edge • State waveform display • Post-processing MSO feature • Timing Core • Best for measurements across multiple time domains • Almost no impact on design timing • Measurements include skew from routing path variancesGlitch detection • Measured per MSO timing sample rate

11. The thick lines show the FF's and routes added by ATC2 Since there is a FF "in the fabric" in addition to one at the I/O buffer, the router can use timing solely within the ATC2 core to move across the chip State Cores…always have multiple pipeline stages to minimize timing impact Probe point Output Pin Customer Logic FF ATC2 (1 signal) FF FF FF

12. Technology Walk Through (Xilinx Example) • Xilinx Core Inserter • Create core & put it in design • Agilent FPGA Dynamic Probe • Pin and signal/bus setups • Core control • Taking measurements

13. Demo #1- Packet Flow Demo (MSO_comm_v9.bit) Measure in 4 different parts of communication system in a few seconds

14. Target System – Xilinx XC2V250 JTAG Mictor Connector (plug MSO cable into EVEN side)

15. 2. FPGA Dynamic Probe SW application integrated with Infiniium 4. Probe core output 3. Control access to new signals via JTAG 1. Insert ATC2 core in FPGA with Xilinx ChipScope Pro

16. Define 1st Bank to View Transmit Side External Data IN Monitor Serial Packets 8B/10B Encoder “Serial to Monitor” State Machine “Serial from Monitor” State Machine State TID Out Serial Acks State TID Ack ID Master State Machine 8 7 RAM Xilinx FPGA Bank 0 Bank 3 Bank 2 Bank 1 TID State Data In & Out Master State Mach. Ack ID State TID out Micro Blaze uP Agilent Trace Core 2 MUX External RAM JTAG to MSO or PC To MSO digital Connection (15 Pins for Debug + clk)

17. Define 2nd Bank to View Receive Side External Data IN Monitor Serial Packets 8B/10B Encoder “Serial to Monitor” State Machine “Serial from Monitor” State Machine TID Out Serial Acks State Ack ID Master State Machine 5 3 RAM 7 Xilinx FPGA Bank 0 Bank 3 Bank 2 Bank 1 TID State Data In & Out Master State Mach. Ack ID State TID out Micro Blaze uP Agilent Trace Core 2 MUX External RAM JTAG to MSO or PC To MSO digital Connection (15 Pins for Debug + clk)

18. Define 3rd Bank to View 8B/10B Encoder External Data IN Monitor Serial Packets 8B/10B Encoder “Serial to Monitor” State Machine “Serial from Monitor” State Machine State TID Out Serial Acks State TID Ack ID 5 Master State Machine 10 RAM Xilinx FPGA Bank 0 Bank 3 Bank 2 Bank 1 TID State Data In & Out Master State Mach. Ack ID State TID out Micro Blaze uP Agilent Trace Core 2 MUX External RAM JTAG to MSO To MSO digital Connection (15 Pins for Debug + clk)

19. 4th Bank to View Master State Machine External Data IN Monitor Serial Packets 8B/10B Encoder “Serial to Monitor” State Machine “Serial from Monitor” State Machine State TID Out Serial Acks State TID Ack ID Master State Machine 15 RAM Xilinx FPGA Bank 0 Bank 3 Bank 2 Bank 1 TID State Data In & Out Master State Mach. Ack ID State TID out Micro Blaze uP Agilent Trace Core 2 MUX External RAM JTAG to MSO To MSO digital Connection (15 Pins for Debug + clk)

20. 4 Signal Banks External Data IN Monitor Serial Packets 8B/10B Encoder “Serial to Monitor” State Machine “Serial from Monitor” State Machine State TID Out Serial Acks State TID Ack ID 5 Master State Machine 8 7 10 5 3 15 RAM 7 Xilinx FPGA Bank 0 Bank 3 Bank 2 Bank 1 TID State Data In & Out Master State Mach. Ack ID State TID out Micro Blaze uP Agilent Trace Core 2 MUX External RAM JTAG to MSO To MSO digital Connection (15 Pins for Debug + clk)

21. ChipScope Pro • ILA & logic analyzer viewer • Core Inserter • Post-synthesis insertion • Core Generator • Pre-synthesis core generation Preferred design flow:

22. Inserting ATC2 Cores Design Entry .v . vhd Functional Simulation Synthesis . edf Post-synthesis Simulation .sfp .sdc Insert ATC 2 Cores Xilinx Core Inserter Timing Constraints . edf . ngo . cdc Translate (LUTs and nets) .ucf Map (LUTs into Slices) Place&Route Place&Route (FPGA resources) (FPGA resources) ISE ISE . ncf . pcf Static Timing Timing Simulation Static Timing FPGA Editor Analysis Analysis ISE ISE • Minor Design Modifications • FPGA Editor Program FPGA Program FPGA ISE Impact ISE Impact mcs .bit . Bitstream PROM FPGA

23. Pin compression # of debug pins # of signal banks ATC2 pin location Set Core Parameters Xilinx Core Inserter Select Capture Mode

24. Select Bank Add signals into each desired Bank Xilinx Core Inserter: Specify Signal Bank Grouping

25. Enable Integrated FPGA Dynamic Probe Application

26. Auto Pin mapping Map physical connection between core & scope Look for test pattern on each pin PC Board FPGA 1. Send “training pattern” over a ATC2 pin one at a time ATC2 with auto-setup ATC3 JTAG

27. CLK output data outputs Valid state Valid state Valid state Triggering on Valid StatesATCK (clock) + Pattern guarantees valid state This design transitions on positive clock edge, so data should be stable on negative clock edges.

28. Trigger on Bus2 = 02H and D15 (atck) falling edge clk B2

29. Symbols Readouts

30. Transforming Timing (asynchronous) Waveforms… into State (synchronous) Waveforms Invalid state (happens on rising edge when design is transitioning)

31. State Clock:D15 is the ATCK, data will be stable on the falling edge

32. Resulting State Waveforms Invalid states are filtered out (post-processing)

33. Demo #2- Up down counter (MSO_up_down_20MHz.bit) Measure in 2 different parts of Xilinx system in a few seconds

34. Target System – Xilinx XC2V250 JTAG Mictor Connector (plug MSO cable into ODD side)

35. 2. FPGA Dynamic Probe SW application runs on PC PC and MSO 6000 connect via LAN/USB/GPIB/etc 4. Probe core output 3. Control access to new signals via JTAG 1. Insert ATC2 core in FPGA with Xilinx ChipScope Pro

36. ATC2 core configured with 2 Signal Banks 8 bit Count Down Design 8 bit Count Up Design 8 8 Xilinx FPGA Bank 0 Bank 1 Agilent Trace Core 2 MUX To MSO digital Connection (8Pins for Debug + clk) JTAG to MSO

37. Run the MSO FPGA Dynamic Application on PCPC connects to MSO6000 via LAN, USB, or GPIB

38. FPGA Dynamic Probe

39. Auto Pin Mapping 3. Map physical connection between core & scope 2. Look for test pattern on each pin PC Board FPGA 1. Send “training pattern” over a ATC2 pin one at a time ATC2 with auto-setup ATC3 JTAG

40. Pin Mapping MSO signals do not connect here. ATCK (clock) should be routed to any other place assessed by MSO digital channels.

41. Select Bank 0 (count up & clock)

42. Count Up Bus & Signal names

43. Select New Set of Internal Signals for Measurement

44. Resulting Measurement Time correlation with external events Bus & Signal names

45. State Triggering: Pattern + ATCK edgeEliminates the potential of triggering on invalid states when FPGA design is transitioning State Triggering

46. Measuring Valid States Invalid state (FPGA design is transitioning on positive clock edge Valid states on falling clock edge

47. N5397A 8000 Series FPGA Dynamic Probe for Xilinx

48. N5406A 6000 Series FPGA Dynamic Probe for Xilinx