Developing Video Applications on Xilinx FPGAs

1. Developing Video Applications on Xilinx FPGAs Xilinx Confidential

2. Xilinx Design FlowVideo Hardware Development Xilinx / Avnet / Mathworks Video Seminar

3. Simulink Executable Spec • Purely algorithmic • Use abstract blocks • Define desired system response Xilinx / Avnet / Mathworks Video Seminar

4. Executable Spec Demo Xilinx / Avnet / Mathworks Video Seminar

5. Xilinx Design FlowVideo Hardware Development Xilinx / Avnet / Mathworks Video Seminar

6. Design a Hardware Architecture • Floating-point numbers • Defining basic elements of Hardware Architecture • Compare to Executable Spec Xilinx / Avnet / Mathworks Video Seminar

7. Define Fixed-Point Quantization • Compare fixed-point error to golden source Xilinx / Avnet / Mathworks Video Seminar

8. Redefine Dataflow for Hardware • Convert from frames to serial streaming • Consistent with CMOS video camera outputs Xilinx / Avnet / Mathworks Video Seminar

9. Redefine design using the Xilinx DSP Blockset • Xilinx DSP Blockset includes over 100 DSP building blocks that have been optimized for efficient results on Xilinx devices • Define partition using GatewayIn / GatewayOut blocks Gateway blocks define the FPGA boundary SysGen token block enables use of netlist generation scripts Xilinx / Avnet / Mathworks Video Seminar

10. Model Based Design Demo Xilinx / Avnet / Mathworks Video Seminar

11. Xilinx Design FlowVideo Hardware Development Xilinx / Avnet / Mathworks Video Seminar

12. Video Hardware Verification Flow Golden Input Sequences & Test Cases • The Key is Fast Algorithm Confirmation • Simulink and the Video and Imaging blockset • Early System Architecture • Bit True, Not cycle accurate Reference Model 50+ Test Sequences • Micro-Architecture • IO Definitions • Automated TB Generation • API Definition • Early FPGA Characterization • Test Cases • Pedestrian Crossing • Abandon Object • Privacy Regions • Object Removal Design Capture Golden Test Vector Suite Verification • HDL Simulation • Back Annotated HDL Sim • SysGen CoSim Validation Golden Test Vectors = ? • SysGen-VSK HwCoSim • SysGen-VSK-VFBC HwCoSim • Live Validation, Camera>VSK>Display Xilinx / Avnet / Mathworks Video Seminar

13. Accelerating Verification through Hardware • Hardware co-verification removes simulation bottleneck • Up to 1000x simulation performance improvement • Automates FPGA and board setup process Xilinx / Avnet / Mathworks Video Seminar

14. Eliminating IO Bottlenecks using Hardware Frame Passing System Generator includes specials “Shared Memory Read / Write” blocks to allow large amounts of data to be efficiently passed to hardware from Simulink • Boost HW co-sim performance by bundling input data samples together thus reducing simulation to hardware transactions. • - Frame size =2880 Xilinx / Avnet / Mathworks Video Seminar

15. Simulation Runtime Improvements using Hardware Co-simulation * For bit-true hardware accurate simulation models Xilinx / Avnet / Mathworks Video Seminar

16. Additional Data from Xilinx Video Development Team • Notes: • 100 Mbps Ethernet link, Effective rate ~5.1 Mbps • ML506 Virtex-5 SXT development platform • Payload = 2 * N_Frames * Frame_Size * 32-bits • Load N frames of data, Process N Frames, Store N Frames Xilinx / Avnet / Mathworks Video Seminar

17. Hardware Co-Simulation Demo Xilinx / Avnet / Mathworks Video Seminar

18. Xilinx Design FlowVideo Hardware Development Xilinx / Avnet / Mathworks Video Seminar

19. Why Video Systems? • Video designs generally include embedded processing for: • Video system control and dataflow control • Table and memory updates • Low performance video processing • Xilinx embedded processors allow high-performance video systems on a single chip • Lower cost • Higher performance • Obsolescence proof Xilinx / Avnet / Mathworks Video Seminar

20. Embedded base system provided with the VSK Forms the framework from which video designs are created Includes one MicroBlaze embedded processor Customized using Platform Studio The VSK Base System Xilinx / Avnet / Mathworks Video Seminar

21. System Generator automatically generates DSP accelerators for use with the Xilinx embedded development environment (XPS) placed into embedded IP Catalog Supports PLB or FSL bus Supports async clocking Includes driver files and documentation XPS project can be imported into SysGen for system debug System Generator to Embedded Xilinx / Avnet / Mathworks Video Seminar

22. Video Starter Kit Reference IP • Provided as a library of “drag and drop” IP for use with the video base system • Provides abstraction to the video interface details • Includes SW driver files Platform Studio IP Catalog Reference IP included with the VSK Generated by SysGen Xilinx / Avnet / Mathworks Video Seminar

23. Abstracting the Processor Interface • “Shared” registers, RAMs and FIFOs are used to create HW / SW abstraction • DSP design connects to a “to” or “from” memory • Memory maps and interface logic is added during RTL generation • Software drivers and documentation are created for easy programming Xilinx / Avnet / Mathworks Video Seminar

24. System Design Integration Demo Xilinx / Avnet / Mathworks Video Seminar

25. Video Example #1 - VFBC Xilinx / Avnet / Mathworks Video Seminar

26. Simplest Frame Buffer Data Transfer DVI Input DVI Output Frame Buffer Basic “real-time” video processing Image Processing DVI Input DVI Output “Real-time” Frame Buffer Based Video Processing Image Processing Camera Input DVI Output Frame Buffer Getting Started with VSK Reference Designs Xilinx / Avnet / Mathworks Video Seminar