Review of EI 209 Computer Organization

1. Review of EI 209 Computer Organization Haojin Zhu Associate Professor http://nsec.sjtu.edu.cn/ @朱浩瑾_SJTU (sinaweibo) @Haojin Zhu (Face book)

2. Chapter I: Performance Evaluation • Throughput • Response Time • CPI=clock cycles per instruction • Clock cycle • Instruction Count • Transition from uniprocessor to multi-core (why?) • Amdahl’s law (what is the limit for performance improvement?) • MIPS=million instructions per second

3. Chapter II: Instructions: Language of Computer • MIPS (RISC) Design Principles • Simplicity favors regularity • Smaller is faster • Make the common case fast • Good design demands good compromises • Three kinds of instructions: R type, I type, J type (format) • Handling large constant: lui+ori • Branch destination • Jump destination • Programming is not required in the final

4. Chapter 3: Arithmetic forComputers • 2’s complement, 1’s complement, biased notation • Zero extension vs sign extension • Overflow • Basic multiplication and advanced multiplication algorithm • Booth algorithm (comparison with the shift and add multiplication?) • Restoring division/ non-restoring division (comparision?) • IEEE 754 floating point: single precision, double precision • Representation range and accuracy • Addition and multiplication • Round (e.g., round to nearest even)

5. Chapter 4A: The Single Cycle Processor • Clocking methodology • How to design the processor step by step • Data path for R-type, I-type, LW, SW, branch, jump • Critical path= Longest Delay Path (assignments) • Control Signals for different instructions

6. Chapter 4B: Multi-cycle Datapath • Why need multi-cycle datapath? • Datapath and control signals for different instructions in different stages? • Average CPI • Compare the performance of single cycle and multi-cycle datapath

7. Chapter 4C&D: Pipeline and Data Hazard • Data path in pipelined processor and control signals (see the assignment) • Data Hazard: RAW, WAW, WAR • Handle RAW data hazard • Stall the pipeline: Insert Noop • Forwarding: conditions (special case: load use data hazard) • Handle WAW and WAR • Renaming • Handle Branch • Prediction • Flush (difference between noop and flush?) • Scheduling (Not required in the final) • Exception • Interrupt • Trap

8. Chapter 4E: Multiple-Issue Processor • The techniques for modern processor (understanding the concept is ok) • deeper pipelines: superpipelining • Multi-issue processor: Superscalar • Reduced CPIstall • Diversified pipeline • Out of order execution • Branch prediction • Identify and resolve stalls of RAW, WAW, WAR • Code scheduling (NOT required in this final)

9. Chapter 5: Cache • Principle of locality: Temporal Locality, Spatial Locality • Cache management: Direct mapped, Multiword Block Direct Mapped Cache, Set Associative Cache • Cache field size • Impact of multi-level cache on the performance

10. Example 1: • Here is a series of address references given as word addresses: 2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, and 11. Assuming a directed-mapped cache with four word blocks and a total size of 16 words, and the cache is initially empty. Label each reference in the list as a hitor a miss and show the final contents of the cache.

11. Problem Distribution of the final exam • 1. Performance evaluation (10’) • 2. Multiplication, division and floating point (20’) • 3. Single cycle datapath(10’) • 4. Multiple cycle datapath(10’) • 5. Pipleline and Data dependence (20’) • 6. Cache Management(10’) • 7. Brief answer (20’)

12. Other reminder for final examination • Please pay special attention to examples in slides+ assignments (especially those examples I presented in classes) + text book (at least 1 time) • Time & Location2014-01-09第18周星期四08：00－10:00 东中院3-201,301 • You could bring dictionary, calculator. Other course material is not allowed • Office hour: Tuesday afternoon 1 pm to 4 pm (lab:3-522) • My office : electrical school 3-509 • Contact me by @ 朱浩瑾_SJTU in sinaweibo

13. Best Wishes for you in the finals