Ring BPM Electronics Digitizer, PCI & Timing

Ring BPM ElectronicsDigitizer, PCI & Timing Craig Dawson Ring BPM FDR

BPM Data Flow FIFOs on DFE PCMemory DMA DLL LabVIEW CA Server Communication DLL LabVIEW The PC will be running embedded NT or XP on a solid state disk OtherApplications EPICS Ring BPM FDR

BPMConfiguration • 3 Card system - AFE, DFE and PCI • Timing Module connects through ribbon cable or Twinax • The DFE is a modified version of the Los Alamos DFE with 4 Digitizers & 3 PGAs • The PGAs allow preprocessing of data and communication with the LBUS for control functions Ring BPM FDR

BPM Block Diagram AMPLIFIED SIGNALS FROM PUE DFE PCI DATA ACQUISITION CARD BPM AFE 4 DIGITIZERS AND 2 DATA PGA’s FIFO’s PCI BUS L BUS DECODER PGA & CONTROL SIGNALS L BUS PGA T 0 TRIGGER 2.5 MHzReference 40/10 MHZ PLL CLK SYNTHESIZER 64 Frev clock GAIN SWITCH SIGNALS PROGRAMMABLE PULSE OUTPUTS LO INPUT RTDL TIMING MODULE Event Link Ring BPM FDR

BPM PCIConfigurations • Initially the PCI Card will be the Los Alamos design • We are pursuing a new version that will accommodate higher data rates • If the Digitizers are run at 68 MHz, 4 for data and 1 for status, 16 bits each channel 68MHz * 5*2bytes =680Mbytes/sec Ring BPM FDR

PCI Considerations • 32 bit-33MHz PCI ideally provides 132 Mbytes/sec ( existing ) • 64 bit-64MHz PCI ideally provides 512 Mbytes/ sec ( planned ) • All of the data can’t be available at all times • Timing module functions could be implemented on this board to save cost and improve reliability Ring BPM FDR

Ring BPM Electronics Digitizer, PCI & Timing