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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4. WP1: Giuliana Gangemi WP2: Andr é Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 (09.30 - 17.00 hrs)

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MODERN 1 st Year Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v2.4

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  1. MODERN 1st Year Review ENIAC-120003 MODERNRef. Technical Annex MODERN_PartB Rev2 v2.4 WP1: Giuliana Gangemi WP2: André Juge WP3: Wilmar Heuvelman WP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: June 22, 2010 (09.30 - 17.00 hrs) Review period: 2009-03-01 : 2010-02-28

  2. Agenda • General information (JvG) • Objectives • Consortium • Resources planned and used • Overview of deliverables and milestones status • Cooperation, dissemination and exploitation • Project management: progress, funding problems and amendments • Other issues, Q&A • For WP1 (GG), WP2 (AJ), WP3 (WH), WP4 (DP) and WP5 (LV) • Relationship between workpackages • Progress, highlights and lowlights • Technical status and achievements of deliverables (incl. changes) • Cooperation • Dissemination (publications, patents), exploitation • Other issues, Q&A MODERN 1st Year Review June 22, 2010

  3. Specifically, the main goals of the project are: • Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures. • Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. • Reliability, noise, EMC/EMI. • Timing, power and yield. • Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. • Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) Objectives • The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. MODERN 1st Year Review June 22, 2010

  4. 28 Partners 9 Countries Consortium • The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. MODERN 1st Year Review June 22, 2010

  5. Resources planned and used MODERN 1st Year Review June 22, 2010

  6. Overview of deliverables and milestones status (1) MODERN 1st Year Review June 22, 2010

  7. Overview of deliverables and milestones status (2) MODERN 1st Year Review June 22, 2010

  8. Overview of deliverables and milestones status (3) MODERN 1st Year Review June 22, 2010

  9. Cooperation, dissemination and exploitation MODERN 1st Year Review June 22, 2010

  10. Project management: progress, funding problems and amendments MODERN 1st Year Review June 22, 2010

  11. Other issues Q&A MODERN 1st Year Review June 22, 2010

  12. WP1: Relationship between workpackages MODERN 1st Year Review June 22, 2010

  13. WP1: Progress, highlights and lowlights Task T1.x: Task name Partners (underlined task leader): Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. MODERN 1st Year Review June 22, 2010

  14. WP1: Technical status and achievements of deliverables (incl. changes) MODERN 1st Year Review June 22, 2010

  15. WP1: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when) MODERN 1st Year Review June 22, 2010

  16. WP1: Dissemination (publications, patents), exploitation MODERN 1st Year Review June 22, 2010

  17. WP1: Other issues, Q&A MODERN 1st Year Review June 22, 2010

  18. WP2: Relationship between workpackages MODERN 1st Year Review June 22, 2010

  19. WP2: Progress, high- and lowlights Task T2.x: Task name Partners (underlined task leader): Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. MODERN 1st Year Review June 22, 2010

  20. WP2: Technical status and achievements of deliverables (incl. changes) MODERN 1st Year Review June 22, 2010

  21. WP2: Cooperation WP leader: STF2 If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when) MODERN 1st Year Review June 22, 2010

  22. WP2: Dissemination (publications, patents), exploitation MODERN 1st Year Review June 22, 2010

  23. WP2: Other issues, Q&A MODERN 1st Year Review June 22, 2010

  24. WP3: Relationship between workpackages MODERN 1st Year Review June 22, 2010

  25. WP3: Physical/circuit to RT-level • Objective • PV-aware and PV-robust circuit design techniques and tools, enabling the design of reliable, low cost, low power, low EMI digital and AMS&RF products • Tasks: • PV-aware circuit models • Methodologies, tools and flows for manufacturability, testability, reliability and yield • PV-aware design • Design for low noise and EMI/EMC • Progress: • The activity is on track, and planned deliverables were delivered • milestones are on track • A number of scientific papers were published in 2009 MODERN 1st Year Review June 22, 2010

  26. WP3: Progress, high- and lowlights Task T3.1: PV-aware circuit models Partners:TUD, LIRM, NXP, ST-I, TUE, UNRM Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits. • D3.1.1NXP, ST-I, TUD, TUE, UNRM: Set of alternative symbolic models for lib cells • Highlights • statistical standard cell model based upon statistical transistor models • algorithms to create a transistor-level simulator • Statistical analysis resulted in: • there are four different groups of paths from STA vs SPICE analysis • a novel statistical method has been developed for outlier identification, • a linear mixed model has been developed by taking the random and fixed effects into account for predicting the delay of a path. • Build of VHDL delay models for standard cells which depend on technology parameters, allowing Monte Carlo analysis of variability in delay already at the logic level • Verilog-A modelswhich account also for process, design and operation parameters MODERN 1st Year Review June 22, 2010

  27. T3.1 TUD&TUE&NXP: TL Statistical Standard Cell Models for STA MODERN 1st Year Review June 22, 2010

  28. T3.1 TUD&TUE&NXP: TL Statistical Standard Cell Models for STA MODERN 1st Year Review June 22, 2010

  29. T3.1 UNRM: VHDL Cell delay models MODERN 1st Year Review June 22, 2010

  30. T3.1 STI: Analogue Circuit Models MODERN 1st Year Review June 22, 2010

  31. WP3: Progress, high- and lowlights Task T3.2: Methodologies, tools and flows for manufacturability, testability, reliability and yield Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM To compensate for process variation during circuit design the PV-aware circuit models need to be used in new methods for circuit design and future design tools and flows • D3.2.1 ST-I, UNBO, UNCA, UNRM: Circuit techniques, and speed-up algorithms for PV-aware circuit simulation • Highlights: • Adaptive Body Bias technique has been implemented • First results of an optimization procedure for circuit design • Influence of random process variations on speed and energy consumption has been analyzed • Change of focus: circuit design techniques rather than simulation speed-up techniques MODERN 1st Year Review June 22, 2010

  32. T3.2 UNBO: Adaptive Body Bias techniques MODERN 1st Year Review June 22, 2010

  33. T3.2 UNCA: Influence of random process variations on speed and energy consumption Flip-Flops circuits: (a) TGMS; (b) MC2MOS; (c) SAFF; (d) HLFF; (e) SDFF MODERN 1st Year Review June 22, 2010

  34. T3.2 UNRM STI: optimization procedure for circuit design • First results on on optimization procedure obtained • Performance index can be reduced to 0.021 of first attempt • Learning machines defined: • Artificial Neural Networks • Support Vector Machines MODERN 1st Year Review June 22, 2010

  35. WP3: Progress, high- and lowlights Task T3.3: PV-aware design Partners (underlined task leader):POLI, CSEM, IFXA, LETI, NXP, UPC Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self-timed logic. D3.3.1 CSEM, IFXA, LETI, NXP, POLI, UPC: PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF • Highlights: • new methodologies for the assessment of reliability, including PV and aging • monitor and control strategies on AMS&RF circuits • M&C strategies proposing new PVT monitors • automated monitor insertion methodology • sleep transistors used for power-gating • design strategies for PV tolerant circuits MODERN 1st Year Review June 22, 2010

  36. T3.3 IFX: monitor & control strategies on AMS&RF MODERN 1st Year Review June 22, 2010

  37. T3.3 LETI: PV aware solutions for digital MODERN 1st Year Review June 22, 2010

  38. T3.3 POLI: PV effects in Power-Managed Circuits MODERN 1st Year Review June 22, 2010

  39. T3.3 CSEM&UPC: PV tolerant circuits • The work done by CSEM : • Source biasing • Standard Cell Library using a few cells to provide a better compensation of PV effects • Standard Cell Library using regular layout or restricted design rules, with or without redundancy • Probabilistic CMOS (PCMOS) taking into account that each gate has a probability of failure. • Approximate arithmetic • The work of UPC has involved the following topics: • Regular configurable cell (VCTA) design • Probabilistic evaluation of digital circuits • Approach to digital logic tolerant to noise MODERN 1st Year Review June 22, 2010

  40. WP3: Progress, high- and lowlights Task T3.4: Design for low noise and EMI/EMC Partners:NXP, LIRM, ST-I Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system. D3.4.1 LIRM, ST-IM: Impact of supply noise, and clock distribution on EMI and circuit timing D3.4.2 NXP: RF-interaction models for combined PCB-package-IC • Highlights • Significant attenuation in EM conducted emissions by decoupling insertion & optimization • Successful tape-out following methodology • flow allowing simulating the time domain evolutions of the magnetic emissions • validated by comparing the predicted emissions of two ICs • RF interaction models improved by: Parasitic extraction, De-embedding techniques, package modelling MODERN 1st Year Review June 22, 2010

  41. T3.4 STI&LIRM: magnetic field simulation flow Simulation Measurement MODERN 1st Year Review June 22, 2010

  42. T3.4 NXP: RF interaction models PCB-package-IC MODERN 1st Year Review June 22, 2010

  43. WP3: Technical status and achievements of deliverables (incl. changes) MODERN 1st Year Review June 22, 2010

  44. WP3: Cooperation WP leader: NXP • Collaborations • NXP, TUD, TUE • NXP delivers path delay measurement data, • TUE STA timing correlation • TUD delivers models at transistor level • Regular face-to-face meetings and conference calls • UNIRM UNBO STI TUD • Regular email and material exchange • STI and UNRM face 2 face an almost weekly phone contact • UNBO has strong collaboration with STI • POLI, LETI • Poli relies on Leti to receive tools for var. assessment • CSEM, UPC, LETI, LIRM • Discussions on tolerant circuits and regular layouts • LETI and LIRM have strong collaboration on M&C , regualr phone calls • UPC has contac with LETI and CSEM on temp. mon. and regular layouts • NXP LIRM ST • Conference calls MODERN 1st Year Review June 22, 2010

  45. WP3: Dissemination (publications, patents), exploitation • Accepted: • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "A Simplified Transistor Model for CMOS Timing Analysis", Proceedings of ProRISC 2009 • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis", Proceedings of DAC 2010. • Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Statistical Moment Estimation in Circuit Simulation", Proceedings of VARI 2010 • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor Level Waveform Evaluation for Timing Analysis", Proceedings of VARI 2010. • P. Joubert Doriol, C. Forzan, D. Villa, D. Pandini, R. Castellan, D. Cervini, M. Rotigni, G. Graziosi, G. Contarino, and E. Marzorati, “Power Rail Noise Minimization for EMC-aware Design,” in Proc. SNUG, Mar. 2009. • P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “EMC-aware Design on a Microcontroller for Automotive Applications,” in Proc. DATE, Apr. 2009. • G. Graziosi, P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, and D. Pandini, “Advanced Modeling Techniques for System-level Power Integrity and EMC Analysis,” in Proc. EMPC, Jun. 2009. • C. Forzan and D. Pandini, “Statistical Static Timing Analysis: A Survey,” Integration, the VLSI Journal, vol. 42, pp. 409-435, Jun. 2009. • P. Joubert Doriol, Y. Villavicencio, C. Forzan, M. Rotigni, G. Graziosi, and D. Pandini, “Electromagnetic Interference Reduction on an Automotive Microcontroller,” in Proc. Design Automation Conf., Jul. 2009 • Submitted: • Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs, "Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations", submitted to PATMOS 2010 • Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs, "Noise Analysis of Non-Linear Dynamic Integrated Circuits", submitted to CICC 2010 pdf • Amir Zjajo, Qin Tang, Jose Pineda de Gyvez, Michel Berkelaar, Alessandro Di Bucchianico, Nick van der Meijs, "Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs", submitted to IEEE Transactions on Circuits and Systems-I: Regular Papers. • Amir Zjajo, Manuel Barragan, Jose Pineda de Gyvez, "Process Variation Monitoring Enhanced Calibration and Debugging of Multi-Step Analog to Digital Converters", submitted to IEEE Transactions on Circuits and Systems-I: Regular Papers. MODERN 1st Year Review June 22, 2010

  46. WP3: Other issues, Q&A MODERN 1st Year Review June 22, 2010

  47. WP4: Relationship between workpackages MODERN 1st Year Review June 22, 2010

  48. WP4: Progress, high- and lowlights Task T4.x: Task name Partners (underlined task leader): Explain in a few words: goal of task, what you did this period, what will be delivered and when. Explain in a few words: what went well, better than expected and what went worse than expected; describe corrective actions. MODERN 1st Year Review June 22, 2010

  49. WP4: Technical status and achievements of deliverables (incl. changes) MODERN 1st Year Review June 22, 2010

  50. WP4: Cooperation WP leader: ST-I If strong dependence on partners: list partners, describe dependence Collaboration with partners: list partners, collaboration (division of labor, role, …) Face to face meetings with: list partners (when) Telephone conferences with: list partners (when) MODERN 1st Year Review June 22, 2010

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