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MODERN ENIAC WP2 Meeting. WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron 13:00 – 16:00 pm. Overview D233.
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MODERN ENIAC WP2 Meeting WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron 13:00 – 16:00 pm WP2 Review Meeting Milano, Oct 05, 2011
Overview D233 • Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, IUNET, AMS) • Evaluation of Vt, and Id matching performances of C032/028 RVT devices (STMicroelectronics) • Main mechanisms affective threshold voltage variability investigated through sensitivity analysis (IUNET) • Generation of Correlated Monte Carlo SPICE models (Austria Microsystems AG) • Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (NXP, LETI & IMEP) • Drain current variability and MOSFETs parameters correlations in planar FDSOI (LETI-CEA) • FinFET mismatch in subthreshold region (IUNET& NXP)
Evaluation of Vt, b and Id matching performances of C032/028 RVT devices (STMicroelectronics) Normalized Vt mismatch parameter for (a) NMOS and (b) PMOS, using Vt_Gmmax method in linear mode, Vt_cc in linear mode and Vt_cc in saturated mode AVt 2.8mV.µm for NMOS and 2.5mV.µm for PMOS A 0.6%.µm for NMOS and 0.5%.µm for PMOS 3
Main mechanisms affecting threshold voltage variability investigated through TCAD sensitivity analysis (IUNET) Doping profiles of 32 nm RVT NMOS (a) and PMOS (b) as obtained by STM after calibration with electrical characteristics RDD => AVt=1.5 to 1.8mV.µm LER => AVt=0.75 to 0.9 mV.µm 4
Generation of Correlated Monte Carlo SPICE models (AMS AG) EXP TCAD HV NMOS Ron vs. VTHLIN results for TCAD (left) and measurement (right) SPICE TCAD Histograms for VTH HV NMOS, TCAD (blue, mean 413mV)vs. SPICE Monte Carlo (red, mean 412mV) 5
Drain current variability and MOSFETs parameters correlations in planar FDSOI (LETI-CEA) Benchmark of the on state ID mismatch in FDSOI vs bulk data σ(∆ID/ID) versus gate and drain voltages On-resistance RON for various effective lengths σ(∆ID/ID) comes from σ∆VT and σ∆Ron plus correlation (σ∆Ron related to Rsd) 6
FinFET mismatch in subthreshold region (IUNET) LER for L>55nm Correlation between ΔVth and ΔS as a function of the gate length. For L≥55 nm ΔVth and ΔS are uncorrelated, while for L<55nm a negative correlation is observed A(ΔVth) equal to 2.91mVmm and 2.58mVmm for nFinFET and pFinFET 7
Main conclusions D233 • Vt, , b and Id matching performances of typical C32/28 : • good matching performances, AVt< 3mV.µm, and centered on 0.5%.µm for b (STM). • TCAD 32/28nm Vt variability simulations : major contribution from RDD central part of channel and from LER (IUNET). • A flow for implementing PV simulation results into statistical SPICE models has been presented (AMS). Gaussian distribution shows good agreement with the measurement statistics in terms of correlation. The extraction of covariance matrix and implementation into SPICE was shown. • Variability of drain current (ID) in 6nm thin undoped Silicon-On-Insulator (SOI) MOSFETs studied (LETI & IMEP). ID variations (σID) are found to be highly correlated with both threshold voltage (VT) and ON-state resistance (RON) fluctuations. Improving the access resistances (RSD) enables lowering the RON variability. • Drain current mismatch of FinFET devices in subthreshold, has been studied from both modeling and experimental points of view (IUNET & NXP). Critical length delimits two different mismatch behavior of a FinFET in subthreshold region (Lc=55nm). For L<Lc, both VT and SS fluctuations increase Id variability. 8
